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公开(公告)号：US20250166282A1
公开(公告)日：2025-05-22
申请号：US18900366
申请日：2024-09-27
Applicant: Imagination Technologies Limited
Inventor： Peter Smith-Lacey , Gregory Clark
Abstract: A method of performing intersection testing in a ray tracing system, for a ray with respect to a set of two or more primitives. Each primitive is defined by an ordered set of edges, and each edge is defined by a respective pair of vertices. A set of distinct edges is determined for the set of primitives, each distinct edge being part of at least one primitive of the set of primitives and being defined by a different pair of vertices to the other distinct edges in the set, wherein every edge in the ordered sets of edges that define the set of primitives is represented by a distinct edge of the set of distinct edges. For each distinct edge in the set of distinct edges, an edge test is performed to determine which side of the distinct edge the ray passes on. For each primitive in the set of primitives, a result of the edge test is used for each distinct edge that defines that primitive to determine whether or not the ray intersects that primitive.
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公开(公告)号：US20250166117A1
公开(公告)日：2025-05-22
申请号：US19031815
申请日：2025-01-18
Applicant: Imagination Technologies Limited
Inventor： Robert Brigg , John W. Howson , Xile Yang
Abstract: A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output. Rasterization logic includes second transformation logic configured to re-transform the plurality of untransformed primitives into the plurality of transformed primitives on an untransformed primitive block-basis in accordance with the expansion transformation stage mask for the one or more expansion transformation stages; and logic configured to render the transformed primitives to generate the rendering output.
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公开(公告)号：US20250158798A1
公开(公告)日：2025-05-15
申请号：US19025638
申请日：2025-01-16
Applicant: Imagination Technologies Limited
Inventor： Ravichandra GIRIYAPPA , Vinayak PRASAD , Oana ROSU
Abstract: A time difference between an occurrence of a first event and an occurrence of a second event is estimated. A first time marker indicating the occurrence of the first event and a second time marker indicating the occurrence of the second event are received, wherein at least one event is one of playing a media frame or receiving a beacon. A plurality of delayed versions of the first time marker are provided, each being delayed by a different amount of delay to the other delayed versions. Each of the delayed versions of the first time marker are compared with the second time marker to identify which of the delayed versions of the first time marker is the closest temporally matching time marker to the second time marker. The time difference between the first and second time markers is estimated in dependence on the identified delayed version.
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公开(公告)号：US20250156678A1
公开(公告)日：2025-05-15
申请号：US19024363
申请日：2025-01-16
Applicant: Imagination Technologies Limited
Inventor： Daniel Barnard , Clifford Gibson , Colin McQuillan
Abstract: Input data for a convolutional neural network (CNN) is stored in a buffer comprising a plurality of banks, by receiving input data comprising input data values to be processed in the CNN, determining addresses in the buffer in which the received input data values are to be stored, keeping a cursor for one or more salient positions to reduce arithmetic performed to determine the addresses in the buffer in which the received input data values are to be stored, and storing the received input data values at the determined addresses in the buffer.
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公开(公告)号：US12299412B2
公开(公告)日：2025-05-13
申请号：US17404868
申请日：2021-08-17
Applicant: Imagination Technologies Limited
Inventor： Thomas Ferrere
Abstract: A method and system for processing a set of ‘k’ floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (mi) and an exponent (ei). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (mi). The method includes identifying a maximum exponent (emax) among the exponents ei, aligning the magnitude bits of the numbers (yi) based on the maximum exponent (emax) and processing the set of ‘k’ numbers concurrently.
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Patent Agency Ranking
公开(公告)号：US20250148693A1
公开(公告)日：2025-05-08
申请号：US19017677
申请日：2025-01-12
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Luke T. Peterson
Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.
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公开(公告)号：US20250148264A1
公开(公告)日：2025-05-08
申请号：US19018414
申请日：2025-01-13
Applicant: Imagination Technologies Limited
Inventor： Ivaxi Sheth , Aria Ahmadi , James Imber , Cagatay Dikici
Abstract: A windowed operation is implemented in at least three traversed dimensions. The windowed operation applies a window having at least three dimensions to data having at least three traversed dimensions, with shifts of the window in all three traversed dimensions. Two dimensions of the at least three traversed dimensions are selected, and the windowed operation is mapped to a plurality of constituent 2-D windowed operations in the selected two dimensions, the 2-D windowed operations applying a slice of the window to a slice of the data, with shifts of the slice of the window in only two dimensions. Each of the plurality of 2-D windowed operations is implemented by at least one hardware accelerator, each 2-D windowed operation producing a respective partial result, and the partial results are assembled to produce the result of the windowed operation.
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公开(公告)号：US12266083B2
公开(公告)日：2025-04-01
申请号：US18233815
申请日：2023-08-14
Applicant: Imagination Technologies Limited
Inventor： Ruan Lakemond
Abstract: A method of filtering a target pixel in an image forms, for a kernel of pixels comprising the target pixel and its neighbouring pixels, a data model to model pixel values within the kernel; calculates a weight for each pixel of the kernel comprising: (i) a geometric term dependent on a difference in position between that pixel and the target pixel; and (ii) a data term dependent on a difference between a pixel value of that pixel and its predicted pixel value according to the data model; and uses the calculated weights to form a filtered pixel value for the target pixel, e.g. by updating the data model with a weighted regression analysis technique using the calculated weights for the pixels of the kernel; and evaluating the updated data model at the target pixel position so as to form the filtered pixel value for the target pixel.
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公开(公告)号：US12265450B2
公开(公告)日：2025-04-01
申请号：US18396231
申请日：2023-12-26
Applicant: Imagination Technologies Limited
Inventor： Ian Beaumont
Abstract: A graphics processing system for performing tile-based rendering of a scene that comprises safety-related primitives. The system comprises a plurality of graphics processing units (GPUs), each configured to i) receive tile data identifying one or more protected tiles comprising at least part of a safety-related primitive, ii) process two respective sets of protected tiles, and iii) based on said processing, generate two respective checksums for each respective set of protected tiles. The two respective sets of protected tiles are mutually exclusive, and each respective set and each protected tile being processed by two different GPUs. The system comprises a comparison unit configured to compare one or more pairs of checksums, each pair comprising a respective checksum generated based on a same respective set of protected tiles and generated by different GPUs. The graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
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公开(公告)号：US12259822B2
公开(公告)日：2025-03-25
申请号：US17242028
申请日：2021-04-27
Applicant: Imagination Technologies Limited
Inventor： Dave Roberts , Mario Sopena Novales , John W. Howson
Abstract: A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and whilst each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.
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