Invention Grant
- Patent Title: Reducing parasitic leakages in transistor arrays
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Application No.: US15023752Application Date: 2014-10-07
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Publication No.: US09837450B2Publication Date: 2017-12-05
- Inventor: Stephan Riedel , David Gammie , Boon Hean Pui
- Applicant: FLEXENABLE LIMITED
- Applicant Address: GB Cambridge
- Assignee: FLEXENABLE LIMITED
- Current Assignee: FLEXENABLE LIMITED
- Current Assignee Address: GB Cambridge
- Agency: Sughrue Mion, PLLC
- Priority: GB1317761.3 20131008
- International Application: PCT/EP2014/071468 WO 20141007
- International Announcement: WO2015/052201 WO 20150416
- Main IPC: H01L27/12
- IPC: H01L27/12 ; G09G3/34 ; H03K17/687 ; H01L27/28

Abstract:
A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.
Public/Granted literature
- US20160233254A1 REDUCING PARASITIC LEAKAGES IN TRANSISTOR ARRAYS Public/Granted day:2016-08-11
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