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    Protecting transistor elements against degrading species
    4.
    发明授权
    Protecting transistor elements against degrading species 有权

    公开(公告)号：US10325985B2

    公开(公告)日：2019-06-18

    申请号：US15327263

    申请日：2015-07-21

    Applicant: FLEXENABLE LIMITED

    Inventor： Jan Jongman ,  Anja Wellner ,  Jens Dienelt ,  Karsten Neumann ,  Stephan Riedel

    IPC: H01L29/10 ,  H01L27/32 ,  H01L51/05 ,  H01L51/00

    Abstract: A technique comprising: providing a stack of layers defining at least (a) source and drain electrodes, (b) gate electrode, and (c) semiconductor channel of at least one transistor; depositing one or more organic insulating layers over the stack; removing at least part of the stack in one or more selected regions by an ablation technique; depositing conductor material over the stack in at least the one or more ablated regions and one or more border regions immediately surrounding a respective ablated region; and depositing inorganic insulating material over the stack at least in the ablated regions and the border regions to cover the ablated regions and make direct contact with said conductor material in said one or more border regions all around the respective ablated region.

    Suppressing leakage currents in a multi-TFT device
    5.
    发明授权
    Suppressing leakage currents in a multi-TFT device 有权

    公开(公告)号：US09748278B2

    公开(公告)日：2017-08-29

    申请号：US14901758

    申请日：2014-07-01

    Applicant: FLEXENABLE LIMITED

    Inventor： Stephan Riedel

    IPC: H01L27/12 ,  H01L23/522 ,  H03K17/16

    CPC classification number: H01L27/124 ,  H01L23/5222 ,  H03K17/161 ,  H03K2217/0036

    Abstract: A technique of operating a device comprising a patterned conductor layer defining source electrode circuitry and drain electrode circuitry for a plurality of transistors; a semiconductor layer providing a respective semiconductor channel for each transistor between source electrode circuitry and drain electrode circuitry; and gate electrode circuitry overlapping the semiconductor channels of the plurality of transistor devices for switching the semiconductor channels between two or more levels of conductance; wherein the technique comprises using one or more further conductors independent of said gate electrode circuitry to capacitatively induce a reduction in conductivity of said one or more areas of said semiconductor layer outside of said semiconductor channels.

    Reducing parasitic leakages in transistor arrays
    7.
    发明授权
    Reducing parasitic leakages in transistor arrays 有权

    公开(公告)号：US09837450B2

    公开(公告)日：2017-12-05

    申请号：US15023752

    申请日：2014-10-07

    Applicant: FLEXENABLE LIMITED

    Inventor： Stephan Riedel ,  David Gammie ,  Boon Hean Pui

    IPC: H01L27/12 ,  G09G3/34 ,  H03K17/687 ,  H01L27/28

    CPC classification number: H01L27/1255 ,  G09G3/344 ,  H01L27/124 ,  H01L27/283 ,  H03K17/6874

    Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.

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