Invention Grant
- Patent Title: Optimizing clipping operations in position only shading tile deferred renderers
-
Application No.: US14865200Application Date: 2015-09-25
-
Publication No.: US09846962B2Publication Date: 2017-12-19
- Inventor: Kalyan K. Bhiravabhatla , Subramaniam M. Maiyuran , Saurabh Sharma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop Pruner & Hu, P.C.
- Main IPC: G06T15/30
- IPC: G06T15/30 ; G06T15/80 ; G06T11/40 ; G06T15/00
Abstract:
Marking “Clipped Triangles” as visible triangles for all tiles may be avoided by instead finding an approximate clipping area and marking the triangles as visible only in those tiles in the Position Only Shading Pipe (POSH) pipe. This avoids rendering the triangle in the replay pipe in those tiles where it may not be visible.
Public/Granted literature
- US20170091985A1 OPTIMIZING CLIPPING OPERATIONS IN POSITION ONLY SHADING TILE DEFERRED RENDERERS Public/Granted day:2017-03-30
Information query
