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公开(公告)号：US09836809B2
公开(公告)日：2017-12-05
申请号：US14866437
申请日：2015-09-25
Applicant: Intel Corporation
CPC classification number: G06T1/20 , G06F11/1453 , G06F17/3033 , G06T1/60
Abstract: An apparatus and method for adaptive pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first lookup in a first data structure to identify a second data structure; performing a second lookup in the second data structure using the X and Y coordinates for the pixel block to identify a third data structure; performing a third lookup in a third data structure indexed based on the X and Y coordinates of the pixel block, the third lookup identifying an entry in the third data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and processing the pixel block by the execution cluster.
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公开(公告)号：US20200111454A1
公开(公告)日：2020-04-09
申请号：US16599175
申请日：2019-10-11
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, JR. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G09G5/00 , G06F9/46 , G06F12/0875
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US20170091985A1
公开(公告)日：2017-03-30
申请号：US14865200
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Kalyan K. Bhiravabhatla , Subramaniam M. Maiyuran , Saurabh Sharma
CPC classification number: G06T15/30 , G06T11/40 , G06T15/005 , G06T15/80
Abstract: Marking “Clipped Triangles” as visible triangles for all tiles may be avoided by instead finding an approximate clipping area and marking the triangles as visible only in those tiles in the posh pipe. This avoids rendering the triangle in the replay pipe in those tiles where it may not be visible.
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公开(公告)号：US11508338B2
公开(公告)日：2022-11-22
申请号：US17062871
申请日：2020-10-05
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, Jr. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F12/0875 , G06F9/46 , G09G5/00 , G06F12/084 , G06F12/0811
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US10796667B2
公开(公告)日：2020-10-06
申请号：US16599175
申请日：2019-10-11
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, Jr. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F12/0875 , G06F9/46 , G09G5/00 , G06F12/084 , G06F12/0811
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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Patent Agency Ranking
公开(公告)号：US20190259209A1
公开(公告)日：2019-08-22
申请号：US16286016
申请日：2019-02-26
Applicant: Intel Corporation
Inventor： Kalyan K. Bhiravabhatla , Subramaniam Maiyuran , Robert M. Toth , Tomasz Janczak
Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.
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公开(公告)号：US11087542B2
公开(公告)日：2021-08-10
申请号：US16286016
申请日：2019-02-26
Applicant: Intel Corporation
Inventor： Kalyan K. Bhiravabhatla , Subramaniam Maiyuran , Robert M. Toth , Tomasz Janczak
Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.
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公开(公告)号：US20210125581A1
公开(公告)日：2021-04-29
申请号：US17062871
申请日：2020-10-05
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , Balaji Vembu , Murali Ramadoss , Guei-Yuan Lueh , James A. Valerio , Prasoonkumar Surti , Abhishek R. Appu , Vasanth Ranganathan , Kalyan K. Bhiravabhatla , Arthur D. Hunter, JR. , Wei-Yu Chen , Subramaniam M. Maiyuran
IPC: G09G5/36 , G06F12/0875 , G06F9/46 , G09G5/00
Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
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公开(公告)号：US10546362B2
公开(公告)日：2020-01-28
申请号：US15830860
申请日：2017-12-04
Applicant: Intel Corporation
Abstract: An apparatus and method for adaptive pixel hashing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first lookup in a first data structure to identify a second data structure; performing a second lookup in the second data structure using the X and Y coordinates for the pixel block to identify a third data structure; performing a third lookup in a third data structure indexed based on the X and Y coordinates of the pixel block, the third lookup identifying an entry in the third data structure corresponding to the X and Y coordinates of the pixel block; reading information from the entry identifying an execution cluster to process the pixel block; and processing the pixel block by the execution cluster.
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公开(公告)号：US10235811B2
公开(公告)日：2019-03-19
申请号：US15394027
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Kalyan K. Bhiravabhatla , Subramaniam Maiyuran , Robert M. Toth , Tomasz Janczak
Abstract: An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.
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