Invention Grant
- Patent Title: Forming LED structures on silicon fins
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Application No.: US14906542Application Date: 2013-09-27
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Publication No.: US09847448B2Publication Date: 2017-12-19
- Inventor: Sansaptak Dasgupta , Han Wui Then , Robert S. Chau , Marko Radosavljevic , Benjamin Chu-Kung , Sanaz Gardner
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- International Application: PCT/US2013/062181 WO 20130927
- International Announcement: WO2015/047300 WO 20150402
- Main IPC: H01L33/32
- IPC: H01L33/32 ; H01L27/15 ; H01L33/00 ; H01L33/06 ; H01L33/16 ; H01L33/62 ; H01L33/20 ; H01L21/02

Abstract:
Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon (111) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.
Public/Granted literature
- US20160163918A1 FORMING LED STRUCTURES ON SILICON FINS Public/Granted day:2016-06-09
Information query
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