- Patent Title: Method and apparatus for power reduction in a multi-threaded mode
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Application No.: US15238920Application Date: 2016-08-17
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Publication No.: US09864700B1Publication Date: 2018-01-09
- Inventor: Anthony J. Bybell
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Sunnyvale
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/1027 ; G11C15/00 ; G06F12/0864 ; G06F1/32 ; H04L12/741 ; H04L12/743 ; G06F17/30

Abstract:
A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory is described. The apparatus includes a first input configured to receive a first virtual address corresponding to a first thread, a second input configured to receive a second virtual address corresponding to a second thread, a register bank including a plurality of registers each configured to store a binary word mapped to one of a plurality of physical addresses, a first comparator bank including a first plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration, and a second comparator bank including a second plurality of comparators each coupled to an associated register of the plurality of registers in a fully-associative configuration. An input virtual address to each comparator bank maintains its previous value for when a corresponding thread is not selected.
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