Invention Grant
- Patent Title: Inline measurement of through-silicon via depth
-
Application No.: US14643436Application Date: 2015-03-10
-
Publication No.: US09865514B2Publication Date: 2018-01-09
- Inventor: Hanyi Ding , J. Edwin Hostetter , Ping-Chuan Wang , Kimball M. Watson
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Meisti P.C.
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/304

Abstract:
A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.
Public/Granted literature
- US20150187667A1 INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH Public/Granted day:2015-07-02
Information query
IPC分类: