- Patent Title: Method for reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions
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Application No.: US15439078Application Date: 2017-02-22
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Publication No.: US09917199B2Publication Date: 2018-03-13
- Inventor: Kangguo Cheng , Ramachandra Divakaruni
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/786 ; H01L21/84 ; H01L29/08 ; H01L29/66

Abstract:
A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.
Public/Granted literature
- US20170271525A1 REDUCED PARASITIC CAPACITANCE AND CONTACT RESISTANCE IN ETSOI DEVICES Public/Granted day:2017-09-21
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