Invention Grant
- Patent Title: Apparatus and method for detecting single flip-error in a complementary resistive memory
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Application No.: US15374922Application Date: 2016-12-09
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Publication No.: US09934082B2Publication Date: 2018-04-03
- Inventor: Shigeki Tomishima , Charles Augustine , Wei Wu , Shih Lien L. Lu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: G11C7/02
- IPC: G11C7/02 ; G06F11/07 ; G11C13/00 ; G11C11/16 ; G11C29/42 ; G11C29/52 ; G06F3/06 ; G06F11/10 ; H03M13/15 ; H03M13/37 ; H03M13/00
Abstract:
Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.
Public/Granted literature
- US20170153933A1 APPARATUS AND METHOD FOR DETECTING SINGLE FLIP-ERROR IN A COMPLEMENTARY RESISTIVE MEMORY Public/Granted day:2017-06-01
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