公开(公告)号：US11456281B2

公开(公告)日：2022-09-27

申请号：US16147742

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Yí Li ,  Zhiguo Qian ,  Prasad Ramanathan ,  Saikumar Jayaraman ,  Kemal Aygun ,  Hector Amador ,  Andrew Collins ,  Jianyong Xie ,  Shigeki Tomishima

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/00

Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

公开(公告)号：US10552257B2

公开(公告)日：2020-02-04

申请号：US15737202

申请日：2016-06-02

Applicant: Intel Corporation

Inventor： Helia Naeimi ,  Wei Wu ,  Shigeki Tomishima ,  Shih-Lien Lu

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G11C11/16 ,  G11C29/04

Abstract: Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

公开(公告)号：US20190227871A1

公开(公告)日：2019-07-25

申请号：US16375362

申请日：2019-04-04

Applicant: Intel Corporation

Inventor： Wei Wu ,  Rajesh Sundaram ,  Chetan Chauhan ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F11/10 ,  G06F3/06

Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.

公开(公告)号：US09830988B2

公开(公告)日：2017-11-28

申请号：US15187646

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Wei Wu ,  Shigeki Tomishima ,  Shih-Lien L. Lu ,  James W. Tschanz

IPC: G11C13/00 ,  G11C11/16 ,  G11C7/10

CPC classification number: G11C13/0069 ,  G11C7/1006 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.

公开(公告)号：US09804793B2

公开(公告)日：2017-10-31

申请号：US15277182

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Kuljit S. Bains

IPC: G11C7/00 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C16/20

Abstract: Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations of column select lines of one or more blocks of memory to cause bit values or contents of the one or more blocks to have or store a value of 0.

公开(公告)号：US09600183B2

公开(公告)日：2017-03-21

申请号：US14493130

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Shih-Lien L. Lu

IPC: G06F3/06 ,  G11C7/10 ,  G11C15/00

CPC classification number: G06F3/061 ,  G06F3/0665 ,  G06F3/0689 ,  G11C7/1006 ,  G11C7/1072 ,  G11C15/00

Abstract: Techniques and mechanisms for determining comparison information at a memory device. In an embodiment, the memory device receives from a memory controller signals that include or otherwise indicate an address corresponding to a memory location of the memory device. Where it is determined that the signals indicate a compare operation, the memory device retrieves data stored at the memory location, and performs a comparison of the data to a reference data value that is included in or otherwise indicated by the received signals. The memory device sends to the memory controller information representing a result of the comparison. In another embodiment, a memory controller provides signals to control a compare operation by such a memory device.

公开(公告)号：US12191135B2

公开(公告)日：2025-01-07

申请号：US17132908

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shigeki Tomishima

IPC: H01L21/02 ,  H01L21/4763 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.

公开(公告)号：US11868665B2

公开(公告)日：2024-01-09

申请号：US17681512

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Nilesh N. Shah ,  Chetan Chauhan ,  Shigeki Tomishima ,  Nahid Hassan ,  Andrew Chaang Ling

IPC: G11C13/00 ,  G06F3/06 ,  G06N5/04

CPC classification number: G06F3/0679 ,  G06F3/0613 ,  G06F3/0644 ,  G06N5/04 ,  G11C13/0004 ,  G11C13/0007

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

公开(公告)号：US11301167B2

公开(公告)日：2022-04-12

申请号：US16414265

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F3/06 ,  H03M13/29 ,  H03M13/00 ,  G06F3/00 ,  G11C7/10 ,  G06F11/10 ,  G06N3/08

Abstract: Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.

公开(公告)号：US20220075684A1

公开(公告)日：2022-03-10

申请号：US17530281

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Wei Wu ,  Rajesh Sundaram ,  Shigeki Tomishima

IPC: G06F11/10 ,  G06F11/07

Abstract: Technologies for preserving error correction capability in compute-near-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.