CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same

Invention Grant

US09935107B2 CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same 有权

Patent Title: CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same
Application No.: US15024347

Application Date: 2013-12-16
Publication No.: US09935107B2

Publication Date: 2018-04-03
Inventor: Stephen M Cea , Roza Kotlyar , Harold W Kennel , Kelin J Kuhn , Tahir Ghani
Applicant: INTEL CORPORATION
Applicant Address: US CA Santa Clara
Assignee: Intel Corporation
Current Assignee: Intel Corporation
Current Assignee Address: US CA Santa Clara
Agency: Jordan IP Law, LLC
International Application: PCT/US2013/075437 WO 20131216
International Announcement: WO2015/094164 WO 20150625
Main IPC: H01L27/092
IPC: H01L27/092 ; H01L29/04 ; H01L29/78 ; H01L29/66 ; H01L29/10 ; H01L21/8238

Abstract:

Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.

Public/Granted literature

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L27/00	由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件（其零部件入H01L23/00，H01L29/00至H01L51/00；由多个单个固态器件组成的组装件入H01L25/00）
H01L27/02	.包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的；包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的
H01L27/04	..其衬底为半导体的
H01L27/08	...只包括有一种半导体组件的
H01L27/085	....只包含场效应的组件
H01L27/088	.....有绝缘栅场效应晶体管的组件
H01L27/092	......互补MIS场效应晶体管