One embodiment relates to a pulse latch that includes a latch control logic circuit and a pulse latch circuit. The latch control logic circuit generates a plurality of control signals and selects a control signal of the plurality of control signals to output to the pulse latch circuit. Each control signal of the plurality of control signals causes the pulse latch circuit to operate in a different operating mode. Another embodiment relates to a method of generating control signaling for a pulse latch. A clock signal and a shifted clock signal are received. A plurality of inputs to a multiplexor are generated using the clock signal and the shifted clock signal. An input of the plurality of inputs is selected as an output of the multiplexor. The input is selected by the multiplexor using a plurality of multiplexor configuration bits.