An output stage circuit comprises: a power inverter, coupled to a signal terminal; and a dynamic bias circuit, wherein the dynamic bias circuit connects between a system voltage terminal and the power inverter. The dynamic bias circuit comprises at least one Zener diode, which is configured to maintain a voltage difference between a gate terminal and a source terminal of at least one transistor of the power inverter within a first absolute value; which is configured to maintain a voltage difference between the gate terminal and a drain terminal of the at least one transistor within a second absolute value; and configured to maintain a voltage difference between the drain terminal and the source terminal of the at least one transistor within the second absolute value.