In accordance with embodiments disclosed herein, there is provided systems and methods for time offset validation of components with independent silicon clocks. A requesting component includes transmission logic to transmit timing protocol requests to a responding component, receiving logic to receive timing protocol responses, replay detection logic to detect a retransmission of a timing protocol message and to set an internal timing state of the requesting component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the requesting component as valid. A responding component includes receiving logic, transmission logic, replay detection logic to detect a retransmission of a timing protocol message and set an internal timing state of the responding component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the responding component as valid.