公开(公告)号：US20180173635A1

公开(公告)日：2018-06-21

申请号：US15698180

申请日：2017-09-07

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC: G06F12/0875

CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

公开(公告)号：US20040015533A1

公开(公告)日：2004-01-22

申请号：US10418113

申请日：2003-04-18

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig C. Hansen ,  Alexia Massalin

IPC: G06F007/38

CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/3869 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2207/382 ,  G06F2207/3828 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

Abstract translation: 描述了一种提高乘法器和加法器阵列对低精度运算的利用率的乘法器阵列处理系统。 定义了新的指令，它们作为单个指令的结果提供了额外的乘法和加法操作的部署，以及在符号大小减少时部署更大的乘法和加法操作数。

公开(公告)号：US20180032312A1

公开(公告)日：2018-02-01

申请号：US15224176

申请日：2016-07-29

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC: G06F7/523 ,  G06F7/504

CPC classification number: G06F7/523 ,  G06F7/5045 ,  G06F7/5443 ,  G06F2207/3828

Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.

公开(公告)号：US20040205323A1

公开(公告)日：2004-10-14

申请号：US10757524

申请日：2004-01-15

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F009/44

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可操作以解码和执行指定数据选择操作数的单个指令，以及提供多个数据元素的第一和第二寄存器，所述数据选择操作数包括多个 每个字段选择多个数据元素中的一个，所述执行单元可操作以将由数据选择操作数的每个字段选择的数据元素提供到预期结果的预定位置。

公开(公告)号：US20040156248A1

公开(公告)日：2004-08-12

申请号：US10716561

申请日：2003-11-20

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G11C007/00

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.

Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来操作以解码和执行指令集中的单个指令来提高处理器的性能，所述指令集包括：（a）对寄存器的分割字段中的多个数据元素进行操作的组指令， 连接结果，（b）对齐的存储器操作，其在存储器和寄存器之间移动数据，存储器操作数对齐，以及（c）存储器操作数未对齐的未对齐的存储器操作。

公开(公告)号：US20040049663A1

公开(公告)日：2004-03-11

申请号：US10436340

申请日：2003-05-13

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F009/00

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: The present invention provides a system and method for expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. Operands are provided which are substantially larger than the data path width of the processor. A general purpose register is used to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction. Further execution of the instruction or other similar instructions that specify the same memory address can read the dedicated storage to obtain the operand value. However, such reads are subject to conditions to verify that the memory operand has not been altered by intervening instructions. If the memory operand remains current, the memory operand fetch can be combined with one or more register operands in the functional unit, producing a result. The size of the result is, typically, constrained to that of a general register so that no dedicated or other special storage is required for the result.

Abstract translation: 本发明提供一种用于将至少一个源操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度的系统和方法。 提供了比处理器的数据路径宽度大得多的操作数。 通用寄存器用于指定至少可以读取数据的数据路径宽度至少多于一个的存储器地址。 在指令的初始执行时，数据路径功能单元用专用存储器进行扩充，存储器操作数被复制到该存储器操作数。 指定相同存储器地址的指令或其他类似指令的进一步执行可以读取专用存储器以获得操作数值。 然而，这样的读取受到条件的限制，以验证内存操作数没有被干预指令改变。 如果存储器操作数保持当前，则存储器操作数获取可以与功能单元中的一个或多个寄存器操作数组合，产生结果。 结果的大小通常限制为通用寄存器的大小，因此不需要专用或其他特殊存储。

公开(公告)号：US10204055B2

公开(公告)日：2019-02-12

申请号：US15698180

申请日：2017-09-07

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/0875 ,  G06F9/34 ,  G06F9/38

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

公开(公告)号：US20160321071A1

公开(公告)日：2016-11-03

申请号：US15147811

申请日：2016-05-05

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明提供了通过使用通用寄存器的内容来实质上大于处理器的数据路径的操作数，以指定可读取或写入数据的多个数据路径宽度的存储器地址，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

公开(公告)号：US20150378734A1

公开(公告)日：2015-12-31

申请号：US14749955

申请日：2015-06-25

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

Abstract translation: 公开了可扩展地广泛的操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。

公开(公告)号：US20040210746A1

公开(公告)日：2004-10-21

申请号：US10757516

申请日：2004-01-15

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F009/00

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.

Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来操作以解码和执行指定掩模和包含数据的寄存器的单个指令来提高处理器的性能，该掩码包括各自对应于寄存器中包含的数据的字段的字段 所述执行单元可操作以将所述掩模的一些场检测为具有预定值，并将包含在所述寄存器中的数据的相应字段识别为可写入数据字段; 并使写入使能的数据字段被写入指定的存储器位置。