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公开(公告)号：US20180173635A1
公开(公告)日：2018-06-21
申请号：US15698180
申请日：2017-09-07
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F12/0875
CPC classification number: G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
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公开(公告)号：US10204055B2
公开(公告)日：2019-02-12
申请号：US15698180
申请日：2017-09-07
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F12/08 , G06F9/30 , G06F12/0875 , G06F9/34 , G06F9/38
Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
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3.发明申请公开(公告)号：US20160321071A1
公开(公告)日：2016-11-03
申请号：US15147811
申请日：2016-05-05
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/30
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明提供了通过使用通用寄存器的内容来实质上大于处理器的数据路径的操作数，以指定可读取或写入数据的多个数据路径宽度的存储器地址，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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公开(公告)号：US20150378734A1
公开(公告)日：2015-12-31
申请号：US14749955
申请日：2015-06-25
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
Abstract translation: 公开了可扩展地广泛的操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。 可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序 并在宽缓存中使用操作数。
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公开(公告)号：US20180032312A1
公开(公告)日：2018-02-01
申请号：US15224176
申请日：2016-07-29
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F7/523 , G06F7/5045 , G06F7/5443 , G06F2207/3828
Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
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Patent Agency Ranking
公开(公告)号：US10365926B2
公开(公告)日：2019-07-30
申请号：US15147811
申请日：2016-05-05
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/30 , G06F9/38 , G06F9/35 , G06F9/455 , G06F12/02 , G06F17/50 , H03M13/15 , H03M13/41 , G06F9/448 , G06F9/44 , G03F1/36
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
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公开(公告)号：US20190065149A1
公开(公告)日：2019-02-28
申请号：US16150224
申请日：2018-10-02
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
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公开(公告)号：US10120649B2
公开(公告)日：2018-11-06
申请号：US15224176
申请日：2016-07-29
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
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公开(公告)号：US09785565B2
公开(公告)日：2017-10-10
申请号：US14749955
申请日：2015-06-25
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F12/08 , G06F12/0875
CPC classification number: G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
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10.发明授权Processor for executing wide operand operations using a control register and a results register 有权使用控制寄存器和结果寄存器执行宽操作数操作的处理器公开(公告)号：US09378018B2
公开(公告)日：2016-06-28
申请号：US14828131
申请日：2015-08-17
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
CPC classification number: G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4484 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明提供了通过使用通用寄存器的内容来实质上大于处理器的数据路径的操作数，以指定可读取或写入数据的多个数据路径宽度的存储器地址，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。
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