Abstract:
A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform and recess for defining a second gap having a different size from the first gap.
Abstract:
A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.
Abstract:
A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.
Abstract:
A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.
Abstract:
A one terminal capacitor interface circuit (40) for sensing the capacitance of a capacitor (52) includes a differential integrating amplifier (44) having an input common mode voltage and two summing nodes (66) and (68) whose voltage is substantially equal to the input common mode voltage, a switching circuit (57) for charging the capacitor (52) to a first voltage level (Vx) in a first phase(Phl ), connecting, in a second phase (Ph2), the capacitor (52) to one of the summing nodes (66) of the differential amplifier (44) to provide a first output (Vop); charging the capacitor (52) to a second voltage level (Vz) in a third phase (Ph3), and connecting, in a fourth phase (Ph4), the capacitor (52) to the other summing node (68) of the differential amplifier (44) to provide a second output (Von); the combined first and second outputs (Vop) and (Von), representing the capacitance of the capacitor (52) substantially independent of the input common mode voltage.
Abstract:
A spaced, bumped component structure (10) including a first plate (12), a second plate (14) spaced from the first plate by a first gap (16), a plurality of solder bumps (18)interconnecting the plates and defining the first gap; at least one of the plates having an anomalo section (22) including one of a raised platform (24) and recess for defining a second gap (26) having a different size from the first gap.
Abstract:
A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.