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    Contact member stacking system and method
    1.
    发明申请
    Contact member stacking system and method 有权
    接触件堆垛系统及方法

    公开(公告)号：US20040183206A1

    公开(公告)日：2004-09-23

    申请号：US10814531

    申请日：2004-03-31

    Applicant: Staktek Group, L.P.

    Inventor： James Douglas Wehrly JR.

    IPC: H01L023/48

    CPC classification number: H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules. In a preferred method, a carrier frame of lead frame material is configured to present an opening into which opening project plural lead-like contact members that correspond to the leads of an IC element. The contact members contact the leads of the lower IC element of the stack while the leads of the upper IC of the assembly contact the upper surfaces of the contact members. The stack is assembled using typical surface mount equipment and, after assembly, the carrier portion of the frame is removed to leave the plurality of contact members in place between selected leads.

    Abstract translation: 一种用于选择性堆叠和互连各个集成电路器件以创建高密度集成电路模块的系统和方法。 在优选实施例中，传统的薄小外形封装（TSOP）存储器电路一个在另一个之上垂直堆叠。 组成的IC元件一致地提供大约等于构成组件的IC的容量之和的存储器容量的组合。 堆叠的IC元件通过单独的接触构件电连接，该接触构件连接相邻于IC堆叠的IC元件的相应引线。 在优选实施例中，接触构件由引线框架材料构成。 提供了制造堆叠集成电路模块的方法，其提供合理的成本，批量生产技术来生产模块。 在优选的方法中，引线框架材料的载体框架构造成具有开口，该开口突出了与IC元件的引线相对应的多个引线状接触构件。 接触构件接触堆叠的下部IC元件的引线，而组件的上部IC的引线接触接触构件的上表面。 堆叠使用典型的表面贴装设备组装，并且在组装之后，移除框架的托架部分以使多个接触构件在选定的引线之间就位。

    Point to point memory expansion system and method
    2.
    发明申请
    Point to point memory expansion system and method 审中-公开
    点对点内存扩展系统和方法

    公开(公告)号：US20040245615A1

    公开(公告)日：2004-12-09

    申请号：US10624097

    申请日：2003-07-21

    Applicant: Staktek Group, L.P.

    Inventor： James W. Cady ,  Russell Rapport ,  Julian Partridge ,  James Douglas Wehrly JR. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

    IPC: H01L023/538

    CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

    Abstract: With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. The single memory expansion board is located at the terminus of a transmission line, thus, effectively placing at a relative single point in the addressing system, added memory capacity that would otherwise have required multiple memory expansion boards and, consequently, a longer bus. Therefore, signal degradation issues are mitigated and the system has improved tolerance for higher signal speeds with added memory capacity. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM. Although the present invention is preferably employed to advantage using stacked modules comprised from multiple CSPs, it may be employed with modules comprised from any number and type of integrated circuits including any type of packaging, whether CSP or leaded.

    Abstract translation: 通过使用堆叠模块，提供了用于多个集成存储器电路的点对点寻址的系统和方法。 单个存储器扩展板上装有集成电路的堆叠模块。 单个存储器扩展板位于传输线的终点处，因此，有效地放置在寻址系统中的相对单个点处，增加了否则将需要多个存储器扩展板的存储器容量，并且因此需要更长的总线。 因此，信号降级问题得到缓解，并且具有增加的存储容量的系统已经改善了对更高信号速度的容限。 在优选实施例中，不使用堆叠的四个DIMM插槽存储器存取总线被单个DIMM插槽总线替代，该DIMM插槽总线在单个DIMM上支持堆叠高达四个高。 虽然本发明优选地使用由多个CSP组成的堆叠模块，但是可以使用包括任何数量和类型的集成电路的模块，包括任何类型的封装，无论是CSP还是带引线。

    Contact member stacking system and method
    6.
    发明申请
    Contact member stacking system and method 有权
    接触件堆垛系统及方法

    公开(公告)号：US20020142515A1

    公开(公告)日：2002-10-03

    申请号：US10092104

    申请日：2002-03-06

    Applicant: Staktek Group, L.P.

    Inventor： James Douglas Wehrly JR.

    IPC: H01L021/44

    CPC classification number: H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules. In a preferred method, a carrier frame of lead frame material is configured to present an opening into which opening project plural lead-like contact members that correspond to the leads of an IC element. The contact members contact the leads of the lower IC element of the stack while the leads of the upper IC of the assembly contact the upper surfaces of the contact members. The stack is assembled using typical surface mount equipment and, after assembly, the carrier portion of the frame is removed to leave the plurality of contact members in place between selected leads.

    Abstract translation: 一种用于选择性堆叠和互连各个集成电路器件以创建高密度集成电路模块的系统和方法。 在优选实施例中，传统的薄小外形封装（TSOP）存储器电路一个在另一个之上垂直堆叠。 组成的IC元件一致地提供大约等于构成组件的IC的容量之和的存储器容量的组合。 堆叠的IC元件通过单独的接触构件电连接，该接触构件连接相邻于IC堆叠的IC元件的相应引线。 在优选实施例中，接触构件由引线框架材料构成。 提供了制造堆叠集成电路模块的方法，其提供合理的成本，批量生产技术来生产模块。 在优选的方法中，引线框架材料的载体框架构造成具有开口，该开口突出了与IC元件的引线相对应的多个引线状接触构件。 接触构件接触堆叠的下部IC元件的引线，而组件的上部IC的引线接触接触构件的上表面。 堆叠使用典型的表面贴装设备组装，并且在组装之后，移除框架的托架部分以使多个接触构件在选定的引线之间就位。

    MEMORY EXPANSION AND CHIP SCALE STACKING SYSTEM AND METHOD
    7.
    发明申请
    MEMORY EXPANSION AND CHIP SCALE STACKING SYSTEM AND METHOD 有权
    内存扩展和芯片规模堆叠系统和方法

    公开(公告)号：US20040197956A1

    公开(公告)日：2004-10-07

    申请号：US10709732

    申请日：2004-05-25

    Applicant: Staktek Group L.P.

    Inventor： Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly JR. ,  Jeff Buchle

    IPC: H01L021/44

    CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

    Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载效应。 这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。 在优选实施例中，例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线，以连接到存储器扩展系统中的控制芯片。

    Integrated circuit stacking system and method
    10.
    发明申请
    Integrated circuit stacking system and method 有权
    集成电路堆叠系统及方法

    公开(公告)号：US20030081392A1

    公开(公告)日：2003-05-01

    申请号：US10136890

    申请日：2002-05-02

    Applicant: Staktek Group, L.P.

    Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly JR. ,  Jeffrey Alan Buchle

    IPC: H05K007/10

    CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

    Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP or leaded packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element IC and a support element IC are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two IC elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint occupied by the two ICs. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations in modules provided for high-density memories, high capacity computing, or applications where small size is valued.

    Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到保存PWB或其他板表面积的模块中的技术和结构。 本发明可以用于具有各种尺寸和配置的CSP或带引线的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如管芯尺寸的封装（例如DSBGA）。 在根据本发明设计的优选实施例中，基体元件IC和支撑元件IC通过具有图案化以选择性地连接两个IC元件的至少两个导电层的柔性电路聚集。 连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减少两个IC所占据的总占地面积。 柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。 本发明可用于为高密度存储器，高容量计算或小尺寸的应用提供的模块中的多种配置和组合中的优点。

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