公开(公告)号：US20210109708A1

公开(公告)日：2021-04-15

申请号：US17039108

申请日：2020-09-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Rene Peyrard ,  Fabrice Romain

IPC: G06F7/40

Abstract: An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.

公开(公告)号：WO2020234099A1

公开(公告)日：2020-11-26

申请号：PCT/EP2020/063427

申请日：2020-05-14

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： LABYRE, Jean-Louis

IPC: H04B5/00 ,  G06F13/42 ,  G06K7/10 ,  G06K19/07 ,  G06K19/077 ,  H04B5/02 ,  H04L12/40 ,  H04L12/46 ,  H04W88/10 ,  H04W92/02

Abstract: System, comprising a contactless reader and an apparatus said apparatus including a contactless transponder, said transponder including a contactless interface and a wired interface and being configured to communicate with said reader according to a contactless protocol through said contactless interface, said apparatus including a wired communication bus connected to said wired interface and at least one module connected to said bus, the reader and the transponder being configured so that the reader is the master on said bus during said communication between the reader and the transponder.

公开(公告)号：WO2013167394A1

公开(公告)日：2013-11-14

申请号：PCT/EP2013/058688

申请日：2013-04-26

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： PAIRE, Eric ,  SAUZEDE, Nicolas

IPC: G06F11/36

CPC classification number: G06F11/3664

Abstract: The invention concerns a method of simulating, using a target processor model (112) comprising at least one host processing device, the execution of program instructions on a target processing device (102), the program instructions including at least one transaction instruction associated with a hardware address, each hardware address of said at least one transaction instruction corresponding to one or more trapped memory addresses, said instructions being in the instruction set of said at least one host processing device of said target processor model, the method comprising: executing the instructions of said computer program by said one or more host processing devices of said target processor model, wherein a software trap is generated upon each execution of said at least one transaction instruction; and in response to each software trap, decoding and implementing the transaction instruction causing the software trap.

Abstract translation: 本发明涉及一种使用包括至少一个主机处理设备的目标处理器模型（112）来模拟目标处理设备（102）上的程序指令的执行的方法，所述程序指令包括至少一个与 硬件地址，所述至少一个事务指令的每个硬件地址对应于一个或多个被捕获的存储器地址，所述指令位于所述目标处理器模型的所述至少一个主机处理设备的指令集中，所述方法包括：执行指令 所述计算机程序由所述目标处理器模型的所述一个或多个主机处理设备提供，其中，在每次执行所述至少一个交易指令时产生软件陷阱; 并响应于每个软件陷阱，解码和实现导致软件陷阱的事务指令。

公开(公告)号：WO2012080030A1

公开(公告)日：2012-06-21

申请号：PCT/EP2011/071860

申请日：2011-12-06

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  LAUGA-LARROZE, Christophe

Inventor： LAUGA-LARROZE, Christophe

IPC: H04L12/10 ,  H04N5/765

CPC classification number: H04N21/43635 ,  G09G5/006 ,  G09G2330/02 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/20 ,  H04L12/12 ,  H04N5/765 ,  Y02D50/40

Abstract: An electronic device comprises an output interface having a high data-rate output channel, a medium data-rate bidirectional auxiliary channel, and a power supply relay line; an input interface having a high data-rate input channel, a medium data-rate bidirectional auxiliary channel, and a power supply relay line; and control circuitry designed to organize the relay of a data flow from the input channel towards the output channel, and the relay of data between the auxiliary channels of the input and output interfaces. A power supply system is configured for powering the power supply relay line of one of the interfaces, so-called downstream interface, independently of supplying power to the device. The interfaces and the control circuitry are powered by the power supply relay line of the other interface, so-called upstream interface.

Abstract translation: 电子设备包括具有高数据速率输出通道，中等数据速率双向辅助通道和电源继电器线路的输出接口; 具有高数据速率输入通道，中等数据速率双向辅助通道和电源继电器线路的输入接口; 以及控制电路，其被设计为组织从输入通道到输出通道的数据流的中继，以及在输入和输出接口的辅助通道之间的数据中继。 电源系统被配置为为所述接口之一的所述电源中继线（所谓的下游接口）供电，而与所述设备的供电无关。 接口和控制电路由另一个接口的电源继电器线路（所谓的上游接口）供电。

公开(公告)号：WO2011161338A1

公开(公告)日：2011-12-29

申请号：PCT/FR2011/000361

申请日：2011-06-23

Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (CEA) ,  STMICROELECTRONICS (GRENOBLE 2) SAS ,  JAUD, Marie-Anne ,  GUILLAUMOT, Bernard ,  THOMAS, Olivier

Inventor： JAUD, Marie-Anne ,  GUILLAUMOT, Bernard ,  THOMAS, Olivier

IPC: H01L21/336 ,  H01L29/10 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78

CPC classification number: H01L27/11 ,  H01L27/1104 ,  H01L29/1037 ,  H01L29/66795

Abstract: La cellule mémoire de type SRAM est munie de deux transistors d'accès et de deux inverseurs comportant chacun deux transistors. Un transistor d'accès est associé à un inverseur. Chaque transistor comporte une zone (2) en matériau semi-conducteur formant une saillie depuis une couche (5) en matériau semi-conducteur. La saillie comprend une paroi principale (2a) et une paroi latérale (2b). Chaque transistor comporte une électrode de grille (3', 3") séparée de la zone (2) en matériau semi-conducteur par un matériau isolant de grille. L'électrode de grille (3', 3") recouvre la paroi principale (2a) de la zone (2) en saillie et recouvre partiellement la paroi latérale (2b) de la zone en saillie selon une profondeur de recouvrement. La profondeur de recouvrement des parois latérales est différentes entre les deux transistors (6a) de l'inverseur est également différente de la profondeur de recouvrement du transistor d'accès.

Abstract translation: SRAM存储单元配备有两个存取晶体管和两个每个包括两个晶体管的反相器。 存取晶体管与逆变器相关联。 每个晶体管包括从半导体层（5）突出的半导体区（2）。 突起包括主壁（2a）和侧壁（2b）。 每个晶体管包括通过栅极绝缘体与半导体区域（2）分离的栅电极（3'，3“），栅电极（3'，3”）覆盖突出区域（2）的主壁（2a） 并部分地将突出区域的侧壁（2b）覆盖到覆盖深度。 侧壁的覆盖深度在逆变器的两个晶体管（6a）之间是不同的，并且也不同于存取晶体管的覆盖深度。

公开(公告)号：WO2010142648A1

公开(公告)日：2010-12-16

申请号：PCT/EP2010/057940

申请日：2010-06-07

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  VIGIER-BLANC, Emmanuelle ,  JAFFARD, Jean-Luc

Inventor： VIGIER-BLANC, Emmanuelle ,  JAFFARD, Jean-Luc

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2224/13 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: There is provided a camera module, (50) having an outer surface, which comprises a sensor die, (2) a glass plate, (7) peripheral spacer, (6) and an optical element, (9) where the profile of said outer surface has a shoulder (51) extending around said outer surface in a direction substantially parallel to the plane of said sensor die, (2) and said outer surface is at least partially covered by a deposited metal layer. (24, 32) There is also provided a method of manufacturing a camera module, which comprises the steps of providing an assembly comprising a sensor dice wafer, a spacer wafer and an optical element wafer, said spacer wafer being placed in front of said sensor dice wafer and said optical element wafer being placed in front of said spacer wafer, sawing a top cut, using a first saw blade of a first thickness, proceeding in a direction from said optical element wafer toward said sensor dice wafer, stopping before said sensor dice wafer is reached, and sawing a bottom cut, using a second saw blade of a second thickness, proceeding in a direction from said sensor dice wafer toward said optical element wafer.

Abstract translation: 提供具有外表面的相机模块（50），其包括传感器模具，（2）玻璃板，（7）外围间隔件（6）和光学元件（9），其中所述 外表面具有在基本上平行于所述传感器模具的平面的方向上围绕所述外表面延伸的肩部（51），并且所述外表面至少部分地被沉积的金属层覆盖。 （24,32）还提供了一种制造相机模块的方法，其包括以下步骤：提供包括传感器骰子晶片，间隔晶片和光学元件晶片的组件，所述间隔晶片被放置在所述传感器的前面 骰子晶片和所述光学元件晶片被放置在所述间隔晶片的前面，使用第一厚度的第一锯片从所述光学元件晶片朝向所述传感器骰子晶片的方向切割顶切，在所述传感器 到达骰子晶片，并使用第二厚度的第二锯片从所述传感器晶片晶片朝向所述光学元件晶片的方向锯切底切割。

公开(公告)号：WO2012007519A1

公开(公告)日：2012-01-19

申请号：PCT/EP2011/061986

申请日：2011-07-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  NICOLAS, Marina

Inventor： NICOLAS, Marina

IPC: G06T7/00

CPC classification number: G06T7/0002 ,  G06T2207/30168

Abstract: There is provided a method of measuring the similarity of parts of digital image files (IF1, IF2,IF2-z)), which comprising the steps of calculating a first change value in a similarity between pixel values in a first segment (BIF1a) of a first digital image file (IF1) and in a second segment (BIF1b) of this first file (IF1), said first and second segments of said first file being spatially separated by a first translation vector (td1), calculating a second change value (ν) in the similarity between pixel values in a first segment (BIF2a) of the second digital image file (IF2, IF2-z) and in a second segment (BIF2b) of the second file (IF2, IF2-z), said first and second segment of said second file being spatially separated a second translation vector (td2), wherein the first segment of the first file corresponds to substantially same part of the image as the first segment of the second file and wherein the second segment of the first file corresponds to substantially the same parts of the image as the second segment of the second file, and calculating a structure evolution value indicative of the similarity between the first and second changes.

Abstract translation: 提供了一种测量数字图像文件（IF1，IF2，IF2-z）的部分的相似度的方法，该方法包括以下步骤：计算第一段（BIF1a）中的像素值之间的相似度的第一变化值 第一数据图像文件（IF1）和第一文件（IF1）的第二段（BIF1b）中，所述第一文件的所述第一和第二段在空间上被第一平移向量（td1）分隔，计算第二变化值 （IF2，IF2-z）的第一段（BIF2a）和第二文件（IF2，IF2-z）的第二段（BIF2b）中的像素值之间的相似度（...），所述第二数据图像文件 所述第二文件的第一和第二段在空间上分开第二平移向量（td2），其中第一文件的第一段对应于与第二文件的第一段相比基本上与图像相同的部分，并且其中第二段 第一个文件对应于th的大致相同的部分 e图像作为第二文件的第二段，并且计算指示第一和第二变化之间的相似性的结构演变值。

公开(公告)号：WO2011033342A1

公开(公告)日：2011-03-24

申请号：PCT/IB2009/055093

申请日：2009-09-18

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS Pvt. Ltd. ,  STMICROELECTRONICS (GRENOBLE 2) SAS ,  BUSSON, Pierre ,  CHAWLA, Nitin ,  MEYER, Jacques ,  URARD, Pascal

Inventor： BUSSON, Pierre ,  CHAWLA, Nitin ,  MEYER, Jacques ,  URARD, Pascal

IPC: H04H40/90 ,  H04H20/63

CPC classification number: H04H40/90 ,  H03H17/0213 ,  H03H17/0266 ,  H04H20/63

Abstract: The invention concerns a satellite receive unit having an analog to digital converter (302) adapted to sample a satellite signal to generate a data stream; at least one digital channel multiplexer having at least one processing branch (307A, 307B) which includes: a Fourier transform block (307A, 307B); a channel shifter (310A, 310B); and an inverse Fourier transform block (312A, 312B); the satellite receiver comprising a digital to analog converter (316) adapted to convert the output data stream of the processing branch into an analog signal in a transmission band for transmission over a transmission channel to at least one satellite decoder.

Abstract translation: 本发明涉及一种卫星接收单元，其具有适于采样卫星信号以产生数据流的模数转换器（302）; 至少一个数字信道多路复用器具有至少一个处理分支（307A，307B），其包括：傅立叶变换块（307A，307B）; 一个通道移位器（310A，310B）; 和傅里叶逆变换块（312A，312B）; 所述卫星接收机包括适于将所述处理分支的输出数据流转换成传输频带中的模拟信号的数模转换器，用于通过传输信道传输至至少一个卫星解码器。

公开(公告)号：WO2011001236A1

公开(公告)日：2011-01-06

申请号：PCT/IB2010/001380

申请日：2010-06-04

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  FIANDINO, Maxime

Inventor： FIANDINO, Maxime

IPC: G06T17/50

CPC classification number: G06F17/5022

Abstract: The invention relates to a method for simulating a reset signal in a modeled system comprising a reset control module (RCTL) and a module to be reset (CP), the method comprising emitting by a control thread (IPR) of the control module a reset signal (RST), receiving by the module to be reset the reset signal, waking up a thread (PRC) of the module to be reset, waiting for a reset signal, if the thread (PRC) is waken up by the reset signal, activating a reset exception by the thread (PRC), and if a reset exception is raised, making the thread (PRC) wait for a reboot signal (STT), transmitting the reboot signal by the control thread to the module to be reset, and after receiving the reboot signal, activating the thread (PRC) which executes and waits for a reset signal.

Abstract translation: 本发明涉及一种用于在包括复位控制模块（RCTL）和待复位模块（CP））的建模系统中模拟复位信号的方法，该方法包括由控制模块的控制线程（IPR）发出复位 信号（RST），由模块接收以复位复位信号，唤醒要复位的模块的线程（PRC），等待复位信号，如果线程（PRC）被复位信号唤醒， 激活线程（PRC）的复位异常，如果复位异常引起，使线程（PRC）等待重新启动信号（STT），将控制线程的重启信号发送到要复位的模块，以及 在接收到重新启动信号之后，激活执行并等待复位信号的线程（PRC）。

公开(公告)号：WO2012117232A1

公开(公告)日：2012-09-07

申请号：PCT/GB2012/050236

申请日：2012-02-03

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS ,  RAYNOR, Jeffrey ,  MELLOT, Pascal

Inventor： RAYNOR, Jeffrey ,  MELLOT, Pascal

IPC: G06F3/041

CPC classification number: G06F3/033 ,  G06F3/0304 ,  G06F3/03547 ,  G06F3/038 ,  G06F2203/04101

Abstract: An optical navigation device is provided for detecting movement of a pointer, such as a finger, in three dimensions. A sensor obtains images of the pointer which have been illuminated by an illumination source, and an image scaling module determines the difference in size between images acquired by the image sensor to determine the difference in height of the pointer between images.

Abstract translation: 提供了一种光学导航装置，用于检测诸如手指的指示器在三维中的移动。 传感器获得由照明源照亮的指示器的图像，并且图像缩放模块确定由图像传感器获取的图像之间的尺寸差异，以确定图像之间的指针的高度差。