公开(公告)号：WO2013167394A1

公开(公告)日：2013-11-14

申请号：PCT/EP2013/058688

申请日：2013-04-26

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： PAIRE, Eric ,  SAUZEDE, Nicolas

IPC: G06F11/36

CPC classification number: G06F11/3664

Abstract: The invention concerns a method of simulating, using a target processor model (112) comprising at least one host processing device, the execution of program instructions on a target processing device (102), the program instructions including at least one transaction instruction associated with a hardware address, each hardware address of said at least one transaction instruction corresponding to one or more trapped memory addresses, said instructions being in the instruction set of said at least one host processing device of said target processor model, the method comprising: executing the instructions of said computer program by said one or more host processing devices of said target processor model, wherein a software trap is generated upon each execution of said at least one transaction instruction; and in response to each software trap, decoding and implementing the transaction instruction causing the software trap.

Abstract translation: 本发明涉及一种使用包括至少一个主机处理设备的目标处理器模型（112）来模拟目标处理设备（102）上的程序指令的执行的方法，所述程序指令包括至少一个与 硬件地址，所述至少一个事务指令的每个硬件地址对应于一个或多个被捕获的存储器地址，所述指令位于所述目标处理器模型的所述至少一个主机处理设备的指令集中，所述方法包括：执行指令 所述计算机程序由所述目标处理器模型的所述一个或多个主机处理设备提供，其中，在每次执行所述至少一个交易指令时产生软件陷阱; 并响应于每个软件陷阱，解码和实现导致软件陷阱的事务指令。