公开(公告)号：KR102031174B1

公开(公告)日：2019-10-11

申请号：KR1020120130328

申请日：2012-11-16

Applicant: 삼성전자주식회사

Inventor： 김효중 ,  김병훈 ,  김인영 ,  신상봉 ,  오송하

IPC: H01L27/115 ,  H01L21/8247

公开(公告)号：KR1020140063215A

公开(公告)日：2014-05-27

申请号：KR1020120130328

申请日：2012-11-16

Applicant: 삼성전자주식회사

Inventor： 김효중 ,  김병훈 ,  김인영 ,  신상봉 ,  오송하

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28273 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/11529 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/7881 ,  H01L27/11519

Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device includes a substrate which includes an active region defined by a device isolation pattern, a lower part which is arranged on the substrate and has an upper part and a lower part which has a width wider than that of the upper part, a floating gate which includes a stepped part which is arranged between the upper part and the lower part, a dielectric film which is arranged on the floating gate, and a control gate which is arranged on the dielectric film. The lower part of the floating gate has a height of 4 nm or more.

Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括：衬底，其包括由器件隔离图案限定的有源区;下部，布置在衬底上，并且具有宽度大于上部的宽度的上部和下部;浮动 其包括设置在上部和下部之间的阶梯部分，布置在浮动栅极上的电介质膜和布置在电介质膜上的控制栅极。 浮栅的下部具有4nm以上的高度。

公开(公告)号：KR102065475B1

公开(公告)日：2020-01-13

申请号：KR1020130124143

申请日：2013-10-17

Applicant: 삼성전자주식회사

Inventor： 김효중 ,  오송하 ,  정창구

IPC: H01L21/8247 ,  H01L27/115

公开(公告)号：KR1020150044722A

公开(公告)日：2015-04-27

申请号：KR1020130124143

申请日：2013-10-17

Applicant: 삼성전자주식회사

Inventor： 김효중 ,  오송하 ,  정창구

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/764 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L21/76205 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11526

Abstract: 본발명의일 실시예에따른반도체소자의제조방법은기판에트렌치들및 상기트렌치들사이의상기기판상에하부게이트패턴들을형성하는것, 상기트렌치들을채우는희생패턴들을형성하는것, 상기하부게이트패턴들상에상기희생패턴들의상부면을덮는다공성절연막을형성하는것, 상기다공성절연막에포함된기공들을통해상기희생패턴들을선택적으로제거하여, 상기트렌치들의내벽으로둘러싸인에어갭들을형성하는것, 및상기다공성절연막의상기기공들을통해상기트렌치들의내벽에라이너절연막을형성하는것을포함한다.

Abstract translation: 根据本发明实施例的制造半导体器件的方法包括：在衬底上形成沟槽并在沟槽之间在衬底上形成较低的栅极图案; 形成填充有沟槽的牺牲图案; 形成覆盖下栅极图案上的牺牲图案的上表面的多孔电介质膜; 通过选择性地通过包括在多孔介电膜中的孔隙去除牺牲图案，形成由沟槽的内壁包围的气隙; 以及通过所述多孔介电膜的孔在所述沟槽的内壁上形成衬垫电介质膜。