公开(公告)号：WO2012015606A2

公开(公告)日：2012-02-02

申请号：PCT/US2011044076

申请日：2011-07-14

Applicant: ALTERA CORP ,  DUWEL KEITH ,  ZHENG MICHAEL MENGHUI ,  CHAN VINSON ,  KANKIPATI KALYAN

Inventor： DUWEL KEITH ,  ZHENG MICHAEL MENGHUI ,  CHAN VINSON ,  KANKIPATI KALYAN

IPC: H04J3/16

CPC classification number: H04J3/1682 ,  H04J3/04 ,  H04J3/0685 ,  H04L5/22 ,  H04Q2213/13208 ,  H04Q2213/13322

Abstract: The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

Abstract translation: 本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。 公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。 根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。 这有利地允许优化用于两种类型的通道结合的配置。 在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。 这种去耦有利地消除了先前架构的刚性约束。

公开(公告)号：JP2009153132A

公开(公告)日：2009-07-09

申请号：JP2008322994

申请日：2008-12-18

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： CARVALHO NEVILLE ,  DAVIDSON ALLAN THOMAS ,  TURUDIC ANDY ,  PEDERSEN BRUCE B ,  MENDEL DAVID W ,  KANKIPATI KALYAN ,  ZHENG MICHAEL MENGHUI ,  SHUMARAYEV SERGEY ,  PARK SEUNGMYON ,  HOANG TIM TRI ,  THARMALINGAM KUMARA

IPC: H04L7/033 ,  H03K19/173 ,  H03L7/08 ,  H04L13/08

CPC classification number: H04L25/14

Abstract: PROBLEM TO BE SOLVED: To provide a transceiver system having a reduced latency uncertainty. SOLUTION: The transceiver system has a word aligner with a latency uncertainty of zero. The system also has a bit slipper coupled with the word aligner. The bit slipper slips bits in such a manner that a total delay caused by word alignment of the word aligner and by a bit slip of the bit slipper is constant with respect to all phases of a recovery clock. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供具有减小的等待时间不确定性的收发机系统。

解决方案：收发器系统具有字符对准器，延迟不确定度为零。 该系统还具有与字对准器耦合的位拖鞋。 位拖动器以这样的方式滑动位，使得由字对准器的字对齐引起的总延迟和位拖动器的位滑动相对于恢复时钟的所有相位是恒定的。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：EP2599248A4

公开(公告)日：2017-08-23

申请号：EP11812940

申请日：2011-07-14

Applicant: ALTERA CORP

Inventor： DUWEL KEITH ,  ZHENG MICHAEL MENGHUI ,  CHAN VINSON ,  KANKIPATI KALYAN

IPC: H04L12/28

CPC classification number: H04J3/1682 ,  H04J3/04 ,  H04J3/0685 ,  H04L5/22 ,  H04Q2213/13208 ,  H04Q2213/13322

Abstract: The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

Abstract translation: 本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用率的设备和方法。 公开了一种新的电路架构，其提供可灵活编程以支持多种不同信道绑定方案的电路。 根据本发明的一个方面，新架构将控制信号通道绑定的粒度与数据聚合通道绑定的粒度解耦。 这有利地允许优化两种类型的信道绑定的配置。 在本发明的另一方面，绑定用户信道的逻辑边界与PCS模块的物理边界分离。 这种解耦有利地消除了先前体系结构的刚性约束。