公开(公告)号：WO2012134823A3

公开(公告)日：2013-01-03

申请号：PCT/US2012029212

申请日：2012-03-15

Applicant: ALTERA CORP ,  LI PENG ,  SHUMARAYEV SERGEY Y ,  LONG JON M ,  PHAM TIEN DUC

Inventor： LI PENG ,  SHUMARAYEV SERGEY Y ,  LONG JON M ,  PHAM TIEN DUC

IPC: G02B6/43

CPC classification number: H04J14/02 ,  G02B6/12 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H04B10/40

Abstract: Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.

Abstract translation: 提供了提供具有用于高速关闭设备通信的集成光电子接口的集成电路设备电路的系统。 光电子接口可并入集成电路器件中，释放集成电路器件的部分或全部电I / O引脚。 收发器I / O通道可以设置在可以在电和光收发器I / O通道之间切换的集成电路装置上。

公开(公告)号：WO2012148707A3

公开(公告)日：2012-12-27

申请号：PCT/US2012033481

申请日：2012-04-13

Applicant: ALTERA CORP ,  PEDERSEN BRUCE B

Inventor： PEDERSEN BRUCE B

IPC: H03K19/007 ,  G11C7/24

CPC classification number: G06F21/86 ,  G06F21/76 ,  H03K19/17768

Abstract: Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

Abstract translation: 公开了用于防止可编程集成电路器件的篡改的系统和方法。 通常，可编程器件（如FPGA）具有两个操作阶段; 配置阶段和用户模式阶段。 为了防止可编程设备的篡改和/或反向工程，可以在任何操作阶段中采用各种防篡改技术，以在怀疑篡改之后禁用设备和/或擦除存储在设备上的敏感信息。 一种类型的篡改涉及用许多虚假配置尝试来轰炸设备以便解密加密的数据。 通过使用脏位和粘性错误计数器，设备可以跟踪发生的失败配置尝试次数，并在设备处于配置阶段怀疑篡改时启动防篡改操作。

公开(公告)号：WO2011146453A3

公开(公告)日：2012-01-12

申请号：PCT/US2011036773

申请日：2011-05-17

Applicant: ALTERA CORP ,  SHUMARAYEV SERGEY ,  KOK EDWIN YEW FATT ,  SOH LIP KAI ,  AW CHEE HONG ,  TAN TEE WEE

Inventor： SHUMARAYEV SERGEY ,  KOK EDWIN YEW FATT ,  SOH LIP KAI ,  AW CHEE HONG ,  TAN TEE WEE

IPC: H03K19/0175 ,  H03L7/08 ,  H04L25/02

CPC classification number: H03L7/0805 ,  H03K19/1774 ,  H03K19/17744 ,  H03L7/0891 ,  H03L7/095

Abstract: An integrated circuit includes physical media attachment ("PMA") circuitry that includes two different kinds of transceiver channels for serial data 5 signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively 10 usable as phase-locked loop ("PLL") circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract translation: 集成电路包括物理介质连接（“PMA”）电路，其包括用于串行数据5信号的两种不同类型的收发信道。 一种收发信道用于收发相对低速的串行数据信号。 另一种收发器通道适用于收发相对高速的串行数据信号。 高速通道可选地10可用作锁相环（“PLL”）电路，用于提供其它高速和/或低速通道使用的时钟信号。 低速通道也可以从单独的低速PLL电路获取时钟信号。

公开(公告)号：WO2011119569A3

公开(公告)日：2012-01-05

申请号：PCT/US2011029373

申请日：2011-03-22

Applicant: ALTERA CORP ,  LANGHAMMER MARTIN ,  DHANOA KULWINDER

Inventor： LANGHAMMER MARTIN ,  DHANOA KULWINDER

IPC: G06F17/16 ,  H03K19/173

CPC classification number: G06F17/12 ,  G06F17/16

Abstract: Circuitry for solving linear matrix equations involving a 5 resultant matrix, an unknown matrix and a product matrix that is a product of the resultant matrix and the unknown matrix includes matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, 10 and having a further plurality of resultant matrix elements arranged in columns below the resultant matrix elements on the diagonal. The matrix decomposition circuitry includes an inverse square root multiplication path that computes diagonal elements of the resultant matrix having an inverse square root 15 module, and the said inverse square root module computes inverses of the diagonal elements to be used in multiplication in place of division by a diagonal element. Latency is hidden by operating on each nth row of a plurality of matrices prior to any (n+1)th row.

Abstract translation: 用于求解涉及5个合成矩阵，未知矩阵和作为所得矩阵和未知矩阵的乘积的乘积矩阵的线性矩阵方程的电路包括用于对输入矩阵进行三角测量以产生具有多个结果的合成矩阵的矩阵分解电路 对角线上的矩阵元素10，并且具有排列成对角线上的合成矩阵元素下方的列的另外多个合成矩阵元素。 矩阵分解电路包括反平方根乘法路径，其计算具有反平方根15模块的合成矩阵的对角元素，并且所述反平方根模块计算用于乘法中的对角元素的反转代替除法 对角元素。 通过在任何第（n + 1）行之前的多个矩阵的第n行上操作来隐藏延迟。

公开(公告)号：WO2011112579A3

公开(公告)日：2011-12-22

申请号：PCT/US2011027543

申请日：2011-03-08

Applicant: ALTERA CORP ,  DING WEIQI ,  PAN MINGDE

Inventor： DING WEIQI ,  PAN MINGDE

IPC: H03K3/023 ,  H03K5/08

CPC classification number: H03K3/356139 ,  H03K5/08

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract translation: 高速差分比较器电路具有精确可调的阈值电压。 提供差分参考电压信号来控制比较器的阈值电压。 参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

公开(公告)号：WO2011133565A2

公开(公告)日：2011-10-27

申请号：PCT/US2011033071

申请日：2011-04-19

Applicant: ALTERA CORP ,  LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

IPC: G06F9/455 ,  G06F11/25 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two- dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括诸如传递函数，概率密度函数和眼睛特征的特征函数。 链接仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：WO2010126679A3

公开(公告)日：2011-01-13

申请号：PCT/US2010029860

申请日：2010-04-02

Applicant: ALTERA CORP ,  WORTMAN CURT ,  LEE CHONG H ,  CLIFF RICHARD G

Inventor： WORTMAN CURT ,  LEE CHONG H ,  CLIFF RICHARD G

IPC: G11C7/00 ,  G06F15/76 ,  G11C5/02

CPC classification number: G06F17/5045 ,  G06F2217/84 ,  H03K19/17724 ,  H03K19/17732

Abstract: An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 4OG /10OG Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided.

Abstract translation: 提供集成电路（IC）。 IC包括具有可编程逻辑单元阵列的第一区域。 IC还包括结合到IC中并与第一区域通信的第二区域。 第二区包括标准逻辑单元和基本单元。 在一个实施例中，标准逻辑单元被组合或互连以适应已知协议。 基本单元包括可配置逻辑以适应由基本单元支持的新兴通信协议的修改。 在一个实施例中，第二区域可以嵌入第一区域。 在另一个实施例中，第二区域围绕第一区域的周边限定。 可配置逻辑可以由具有金属掩模可编程互连的混合逻辑元件组成，使得随着新兴通信协议的发展和修改，可以修改IC以适应协议的改变。 在另一个实施例中，可以通过用针对特定应用空间的全新功能替换原始功能来定制通用设备，例如用4OG / 10OG以太网替换用于基于计算的应用的诸如PCI Express的原始功能，例如PCI Express， 因特拉肯，用于有线应用。 还提供了一种设计集成电路的方法。

公开(公告)号：WO2010102007A2

公开(公告)日：2010-09-10

申请号：PCT/US2010026056

申请日：2010-03-03

Applicant: ALTERA CORP ,  STREICHER KEONE ,  LANGHAMMER MARTIN ,  LIN YI-WEN ,  LEUNG WAI-BOR ,  LEWIS DAVID ,  MAUER VOLKER ,  LUI HENRY Y ,  DEMIRSOY SULEYMAN SIRRI ,  YI HYUN

Inventor： STREICHER KEONE ,  LANGHAMMER MARTIN ,  LIN YI-WEN ,  LEUNG WAI-BOR ,  LEWIS DAVID ,  MAUER VOLKER ,  LUI HENRY Y ,  DEMIRSOY SULEYMAN SIRRI ,  YI HYUN

IPC: G06F7/53

CPC classification number: H03K5/1252 ,  G06F7/5324 ,  G06F2207/382 ,  H03K19/17732

Abstract: Digital signal processing ("DSP") circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response ("FIR"), digital filters.

Abstract translation: 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

公开(公告)号：WO2010042447A3

公开(公告)日：2010-07-22

申请号：PCT/US2009059569

申请日：2009-10-05

Applicant: ALTERA CORP ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ATESOGLU ALI

Inventor： SHUMARAYEV SERGEY ,  WONG WILSON ,  CHAN ALLEN ,  ATESOGLU ALI

IPC: H03B5/08 ,  H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

Abstract: An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

Abstract translation: 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和可选导体。 选择导体形成晶体管中的一个与电容器或变容二极管之间的至少一部分连接。

公开(公告)号：WO2007117539A3

公开(公告)日：2008-10-16

申请号：PCT/US2007008469

申请日：2007-04-03

Applicant: ALTERA CORP ,  BURNEY ALI H ,  CHARAGULLA SANJAY K

Inventor： BURNEY ALI H ,  CHARAGULLA SANJAY K

IPC: G06F1/00

CPC classification number: G06F1/10

Abstract: Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay- locked- loop circuit. The delay- locked- loop circuit produces a capture clock that is used to read data from the memory.

Abstract translation: 提供集成电路，例如具有存储器接口电路的可编程逻辑器件集成电路。 存储器接口电路在一系列虚拟读取操作期间测量相关存储器的定时特性。 与系统时钟信号相比，多路复用器和相位检测器用于测量存储器组时钟信号的相移。 存储器接口电路使用这些测量来调整延迟锁定环路。 延迟锁定环路产生捕获时钟，用于从存储器读取数据。