公开(公告)号：JPH065789A

公开(公告)日：1994-01-14

申请号：JP11378891

申请日：1991-04-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAEERE TSUANBURAANO

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78

Abstract: PURPOSE: To optimize current capacity, serial drain resistance and operating voltage of a power stage by providing one or more regions of formed high dopant density, after growing a first epitaxial layer. CONSTITUTION: This method for forming embedded drain or collector region comprises the steps for growing a same conductivity-type first epitaxial layer 2 as that of a substrate 1. The layer 2 has a high density dopant, having lower diffusion coefficient with the same conductivity type as that of the substrate 1 therein. The method further comprises the steps of forming at least one region for constituting an embedded drain region 3 or collector region of a power transistor designed to be connected to the substrate 1. Thus, a boundary between the epitaxial region and the diffused collector region is clarified, and in the case of the series drain resistance or bipolar power transistor, there is no adverse effects on current capacity.