公开(公告)号：JPH09312400A

公开(公告)日：1997-12-02

申请号：JP1285397

申请日：1997-01-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： SARUBUATOORE REONARUDEI

IPC: H01L27/088 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce manufacturing costs by integrating a step wherein isolation regions are formed and a step wherein annular boundary regions are formed into one step wherein doping ions are selectively implanted. SOLUTION: The resistance of an isolation region 6 in proximity to the surface is reduced. For the purpose, the region 6 is reinforced with a p-type doping nucleus in order to minimize contact resistance and improve the entire isolation structure. This is done by using p-type doping implantation. In other words, reinforced regions 30 and base regions 17, or reinforced regions 30 and deep body regions 20, or reinforced regions 30, body, emitter, source and drain regions 21, are simultaneously formed in the same implantation and diffusion step.

公开(公告)号：JPH09298301A

公开(公告)日：1997-11-18

申请号：JP28872996

申请日：1996-10-30

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  FERLA GIUSEPPE

IPC: H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a power device with a higher integration scale than a conventional MOS technique power device. SOLUTION: This device is provided with a conductive insulating gate layer covering a first conductivity type semiconductor layer and a plurality of basic function unit. Each basic function unit contains a slim window formed on an insulating gate layer 9 extending on a slim base body 3. The first conductivity type source regions 60 not doped with impurities of the main parts 40 are alternately positioned in each slim base body 3. Further, a side wall spacer of an insulating material is formed along a longitudinally directed edge of each slim window so as to seal an edge of each slim window. A source metal layer is brought into contact with each slim main body region and each source region through each main body region.

公开(公告)号：JPH08227991A

公开(公告)日：1996-09-03

申请号：JP24323695

申请日：1995-09-21

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： SERUJIYO PARAARA ,  RATSUFUAERE ZANBURAANO

IPC: H01L27/04 ,  H01L27/02 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a circuit by which the electrical continuity of the parasitic component of an integrated circuit can be prevented. SOLUTION: A power supply part 2, a low voltage component which is isolated from the power supply part by an insulating region 7 and a reference voltage region S having a reference voltage are provided. The power supply part 2 has an N-type substrate region D, which is biased by a terminal voltage VD from the reference voltage. The insulating region 7 has P-type conductivity. The low voltage element has an N-type input region 6 connected electrically to an input voltage VIN. Further, electrical continuity lines L1 , L2 and L3 which can be opened and closed by switches are provided between the insulating region 7 and a substrate region D, the input region 6 and the reference voltage region S respectively and the insulating region 7 is electrically connected with the switch to the region, selected from among the substrate region D, the input region 6 and the reference voltage region S to have a lowest voltage.

公开(公告)号：JPH07312372A

公开(公告)日：1995-11-28

申请号：JP14441494

申请日：1994-06-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  LEONARDI SALVATORE ,  CACCIOLA GIOVANNA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

Abstract: PURPOSE: To provide integrated edge structure for a high voltage semiconductor device which does not need dopant of high diffusion coefficient and high temperature diffusion treatment. CONSTITUTION: Integrated edge structure for a high voltage semiconductor device provided with a PN junction formed by first conductivity type diffusion regions 3, 7 stretching from the upper surface of a semiconductor device is provided with the following; a first low doped ring 4 of a first conductivity type which is formed in a first low doped epitaxial layer 2 of a second conductivity type and surrounds the diffusion regions 3, 7, and a second low doped ring 8 of a first conductivity type which is formed in a second low doped epitaxial layer 5 of a second conductivity type formed on the first epitaxial layer 2, superposed on the first ring 4, and fusion-bonded to the ring.

公开(公告)号：JPH07240858A

公开(公告)日：1995-09-12

申请号：JP23539494

申请日：1994-09-29

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

IPC: H03H17/02 ,  H04N5/20

Abstract: PURPOSE: To provide a filter architecture optimizable and easily executable by using fuzzy logic. CONSTITUTION: This filter is provided with a filter circuit 2 for separating high band components and low band components from input signals for video images, a brilliance estimating circuit 6 for obtaining the mean brilliance value of respective plural sections for which the video images are divided, first and second video characteristic adjustment circuits 4 and 5 for changing the high band components and the low band components in response to the mean brilliance value and a totaling circuit 36 for combining the changed high band components and low band components and generating filtered video signals.

公开(公告)号：JPH07221120A

公开(公告)日：1995-08-18

申请号：JP31742292

申请日：1992-11-26

Applicant: CONS RIC MICROELETTRONICA

Inventor： SERUJIO PARAARA

IPC: H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732

Abstract: PURPOSE: To provide a monolithic semiconductor device having a vertical structure with a deep-base and a finger-emitter power transistor having a ballast resistance. CONSTITUTION: This semiconductor device is provided with an epitaxial layer 2 placed one after another on a substrate 3, a base area completed on the epitaxial layer and at least one emitter area 6 for a buried layer for each finger provided with at least one connection area 11 between an emitter and an emitter surface metallization 8, an emitter contact connected to the emitter surface metallization of all fingers, a base and a collector surface metallization 5. At least on connection area 11 existing between at least one emitter area 6 and the emitter surface metallization 8 is formed so as to have a width which provides a proper ballast resistance value(Rv).

公开(公告)号：JPH07201908A

公开(公告)日：1995-08-04

申请号：JP32047394

申请日：1994-12-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： FUERUCHIIO FURISHINA ,  MARUKANTONIO MANJIAGURI

IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78

Abstract: PURPOSE: To prevent receiving effects due to mechanical stresses at the time of wire-bonding an active region of a power semiconductor device. CONSTITUTION: An integrated structure pad assembly for bonding a power semiconductor device chip is provided with a chip part, having a top surface which is completely covered by a metallic layer 10 forming the lower electrode of a power device. The chip part is provided with first sub-parts 1, where the functionally active elements of the power device exist inside. The chip part is provided with at least one second sub-part 11. The active element of the power device does not exist in the second sub-part. The top surface of the metallic layer 10 at the upper part of the second sub-part 11 is made higher than the metallic layer 10 in the first sub-part, and at least one protection part forming a supporting face for bonding wire is formed.

公开(公告)号：JPH07169963A

公开(公告)日：1995-07-04

申请号：JP23350994

申请日：1994-09-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAERU ZANBURANO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

Abstract: PURPOSE: To minimize the effect of a parasitic element by providing a first conductivity-type contact region that is heavily doped, where the first electrode of a first diode is contained at a first conductivity-type epitaxial layer region that has been doped lightly. CONSTITUTION: Each has first and second electrodes and a plural of serially connection diodes D1-D4. The first diode D1 of a plural of diodes has first electrodes 12 and 13 connected to a gate layer 7 of a power device M. The first electrodes 12 and 13 of the first diode D1 have the first conductive-type contact region 12, that is doped has been heavily contained in a first conductivity-type epitaxial layer region that has been doped lightly separated from an epitxial layer 2 that is doped lightly by a second conductivity-type embedded region 14 and a second conductivity-type annular region 15 that is doped heavily, extended from a semiconductor top surface to the embedded region 14, thus minimizing the injection of a carrier from the first electrodes 12 and 13 of the diode D1 to the second electrodes 14 and 15 and at the same time minimizing the gain of a parasitic transistor.

公开(公告)号：JPH07141184A

公开(公告)日：1995-06-02

申请号：JP12784094

申请日：1994-06-09

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： RUSSO BIAGIO ,  POLUZZI RINALDO ,  LUZZI CLAUDIO

IPC: G06F9/44 ,  G05B13/02 ,  G06F1/035 ,  G06N7/02 ,  G06N7/04

Abstract: PURPOSE: To perform an operation at a high calculation speed and at the high degree of a resolution while making a required storage capacity for a hardware to carry out a belonging relation function extremely small. CONSTITUTION: This electronic controller 1A is provided with a buffer part 8 for reproducing the effective value of the belonging relation function and extracting prescribed weight included in the inference rule of fuzzy logic calculation between a storage part 5A for storing a plurality of values of the belonging relation function and the calculation part 6. The storage part 5A is a size corresponding to a large number of non-zero values of the belonging relation function related to a selected point among the finite number of points and the selected point is provided with the maximum number of the non-zero value.

公开(公告)号：JPH07111329A

公开(公告)日：1995-04-25

申请号：JP30736791

申请日：1991-11-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： FUERUTSUCHIO FURIISHINA ,  NERA TABUOORO ,  MARIO RASUPARIISHI

IPC: H01L21/322 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78

Abstract: PURPOSE: To make it possible to constantly keep intrinsic resistance distribution in thickness direction and along the surface of a semiconductor slice by a method wherein the transimplantation of platinum ions is conducted before formation of a contact point and conduction of a metallization process on the backside of a silicon slice against the semiconductor device after a heat process at high temperature. CONSTITUTION: Chemical etching is conducted on the rear surface of a substrate 1, where a total heat treatment process is conducted for the purpose of removing the oxide layer generated as a matter of cource on the rear surface of the substrate 1 where a total heat treatment process is conducted at a high temperature. Subsequently, platinum ions are transplanted. Then, an aperture at contact point reaching the lower layer of source region 4 is formed by etching a passivation oxide 7 for the purpose of providing a window 12. A part of the oxide 7 is left in the amount with which a gate electrode 5 can be insulated from a source metallized layer 9 which is vapor deposited on the whole surface of the device. Thereafter, a metallized layer 11 is vapor deposited on the rear of the substrate 1 for drain metallization. Accordingly, a flat and controlled intrinsic resistance distribution can be formed in thickness direction of a silicon slice.