公开(公告)号：DE60029467D1

公开(公告)日：2006-08-31

申请号：DE60029467

申请日：2000-08-24

Applicant: IBM

Inventor： BASS MITCHELL ,  CALVIGNAC LOUIS ,  GALLO MATTEO ,  HEDDES C MARCO ,  RAO SRIDHAR ,  SIEGEL STEVEN ,  YOUNGMAN ALAN ,  VERPLANKEN JEAN

IPC: G06F13/00 ,  G06F15/16 ,  G06F13/38 ,  G06F13/40 ,  G06F15/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/76 ,  H04L12/56

Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.

公开(公告)号：DE60015186T2

公开(公告)日：2006-02-02

申请号：DE60015186

申请日：2000-12-21

Applicant: IBM

Inventor： BASS MITCHELL ,  CALVIGNAC LOUIS ,  DAVIS TAYLOR ,  GALLO MATTEO ,  HEDDES MARCO ,  JENKINS KENNETH ,  LEAVENS BOYD ,  SIEGEL STEVEN ,  VERPLANKEN JEAN

IPC: G06F9/46 ,  H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60

Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.

公开(公告)号：DE60015186D1

公开(公告)日：2004-11-25

申请号：DE60015186

申请日：2000-12-21

Applicant: IBM

Inventor： BASS MITCHELL ,  CALVIGNAC LOUIS ,  DAVIS TAYLOR ,  GALLO MATTEO ,  HEDDES MARCO ,  JENKINS KENNETH ,  LEAVENS BOYD ,  SIEGEL STEVEN ,  VERPLANKEN JEAN

IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46 ,  H04L29/06

Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.

公开(公告)号：DE60029467T2

公开(公告)日：2007-07-19

申请号：DE60029467

申请日：2000-08-24

Applicant: IBM

Inventor： BASS MITCHELL ,  CALVIGNAC LOUIS ,  GALLO MATTEO ,  HEDDES C ,  RAO SRIDHAR ,  SIEGEL STEVEN ,  YOUNGMAN ALAN ,  VERPLANKEN JEAN

IPC: G06F13/00 ,  G06F15/16 ,  G06F13/38 ,  G06F13/40 ,  G06F15/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/76 ,  H04L12/56

Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.

公开(公告)号：DE60033529D1

公开(公告)日：2007-04-05

申请号：DE60033529

申请日：2000-08-24

Applicant: IBM

Inventor： BASS MITCHELL ,  CALVIGNAC MITCHELL ,  HEDDES MITCHELL ,  PATEL MITCHELL ,  REVILLA MITCHELL ,  SIEGEL MITCHELL ,  VERPLANKEN MITCHELL

IPC: G06F15/16 ,  G06F15/167 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/177 ,  H04L12/56 ,  H04Q11/04

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.