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公开(公告)号：DE60210748T2
公开(公告)日：2007-01-04
申请号：DE60210748
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC LOUIS , HEDDES MARCO , LOGAN FRANKLIN , VERPLANKEN JEAN
Abstract: A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
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公开(公告)号：DE60015186T2
公开(公告)日：2006-02-02
申请号：DE60015186
申请日：2000-12-21
Applicant: IBM
Inventor： BASS MITCHELL , CALVIGNAC LOUIS , DAVIS TAYLOR , GALLO MATTEO , HEDDES MARCO , JENKINS KENNETH , LEAVENS BOYD , SIEGEL STEVEN , VERPLANKEN JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：DE60015186D1
公开(公告)日：2004-11-25
申请号：DE60015186
申请日：2000-12-21
Applicant: IBM
Inventor： BASS MITCHELL , CALVIGNAC LOUIS , DAVIS TAYLOR , GALLO MATTEO , HEDDES MARCO , JENKINS KENNETH , LEAVENS BOYD , SIEGEL STEVEN , VERPLANKEN JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：DE60213430T2
公开(公告)日：2007-08-23
申请号：DE60213430
申请日：2002-05-03
Applicant: IBM
Inventor： BARKER JAMES , CLAUBERG ROLF , CALVIGNAC LOUIS , HERKERSDORF GUENTHER , VERPLANKEN JEAN , WEBB JOHN
Abstract: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
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公开(公告)号：DE60213430D1
公开(公告)日：2006-09-07
申请号：DE60213430
申请日：2002-05-03
Applicant: IBM
Inventor： BARKER JAMES , CLAUBERG ROLF , CALVIGNAC LOUIS , HERKERSDORF GUENTHER , VERPLANKEN JEAN , WEBB JOHN
Abstract: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
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Patent Agency Ranking
公开(公告)号：DE60203380D1
公开(公告)日：2005-04-28
申请号：DE60203380
申请日：2002-01-28
Applicant: IBM
Inventor： BASSO CLAUDE , CALVIGNAC LOUIS , HEDDES MARCO , LOGAN FRANKLIN , VERPLANKEN JEAN
Abstract: Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
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公开(公告)号：DE60029467D1
公开(公告)日：2006-08-31
申请号：DE60029467
申请日：2000-08-24
Applicant: IBM
Inventor： BASS MITCHELL , CALVIGNAC LOUIS , GALLO MATTEO , HEDDES C MARCO , RAO SRIDHAR , SIEGEL STEVEN , YOUNGMAN ALAN , VERPLANKEN JEAN
IPC: G06F13/00 , G06F15/16 , G06F13/38 , G06F13/40 , G06F15/00 , G06F15/173 , G06F15/177 , G06F15/76 , H04L12/56
Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
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公开(公告)号：DE60210748D1
公开(公告)日：2006-05-24
申请号：DE60210748
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC LOUIS , HEDDES MARCO , LOGAN FRANKLIN , VERPLANKEN JEAN
Abstract: A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
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公开(公告)号：DE60203785D1
公开(公告)日：2005-05-25
申请号：DE60203785
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC LOUIS , HEDDES MARCO C O IBM UNITED KI , LOGAN FRANKLIN , VERPLANKEN JEAN
IPC: H04L12/861 , H04L29/06 , H04L12/56
Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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公开(公告)号：DE60029467T2
公开(公告)日：2007-07-19
申请号：DE60029467
申请日：2000-08-24
Applicant: IBM
Inventor： BASS MITCHELL , CALVIGNAC LOUIS , GALLO MATTEO , HEDDES C , RAO SRIDHAR , SIEGEL STEVEN , YOUNGMAN ALAN , VERPLANKEN JEAN
IPC: G06F13/00 , G06F15/16 , G06F13/38 , G06F13/40 , G06F15/00 , G06F15/173 , G06F15/177 , G06F15/76 , H04L12/56
Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
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