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    3.
    发明专利
    未知

    公开(公告)号：DE1151686B

    公开(公告)日：1963-07-18

    申请号：DEJ0016904

    申请日：1959-08-27

    Applicant: IBM

    Inventor： RICE REX ,  RAHENKAMP ROBERT ARTHUR ,  BLAAUW GERRIT ANNE

    IPC: G06F3/06 ,  G06F5/06 ,  G06F9/30 ,  G06F9/315 ,  G06F9/318 ,  G06F9/32 ,  G06F9/40 ,  G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F13/12 ,  G06F15/78 ,  G06F17/30

    Abstract: 926,181. Digital electric calculating. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 9, 1960 [June 11, 1959 (3)], No. 16245/60. Class 106 (1). In a stored programme general purpose computor an instruction word may call up at least a part of a further word, named a control word, in order to complete the information necessary that the operation specified by the instruction word be performed. The main store is a magnetic core matrix into which data from peripheral devices such as magnetic tape stores, punched cards or tape may be read in one half-word at a time and from which data being processed including instruction words is read into three registers having interchangeable functions but of which two may be combined to form upper and lower accumulators. The computer is asynchronous, the completion of one operation leading to the read-out of the instruction word for the next operation from an address specified by an instruction counter. In the main store each word comprises ten alpha-numeric, six-bit (plus parity bit) characters, each character comprising four numeric and two zone bits. An instruction or control word comprises sixteen four-bit numeric characters, compressed to fifteen by limitation of variables and stored as ten six-bit characters by utilizing the zone bits of two characters of a storage word to specify one character of an instruction or control word. Thus the zone bits of characters 0 and 1 of a storage word represent the eleventh character of an instruction and are staticized as such in a register. A data word may be of up to ten characters overlapping two adjacent storage words, and if such a condition exists, known as a split-field, an operation is preceded by assembly of the required data word in one of the registers. A data word may be distinguished by its state which is on if a bit is present in the first zone position of the character 8, off otherwise. The machine is controlled by timers to each of which is allotted a fixed number of time intervals not all of which are used for any particular operations. Thus the arithmetic timer has 28 " times " but in the add operation without split-field only times 5, possibly 6, and 24 are used. The timers jump directly to the times used in the operation being performed. Instructions: format and codes.-An instruction word which is one of the specific types listed below, is in the form of an operation code (two characters), modifier (one character), control (four characters), operand (four characters), index (four characters) and index function (one character). An input-output machine control instruction is defined by an operation code 02 (Fig. 2); the modifier specifies certain machine functions, e.g. modifier 0 will cause control simply to determine if the required machine is busy, modifier 6 will cause a tape mark to be written to indicate end of file; control is not used; operand specifies the unit to which the instruction relates; index specifies the storage address of a control word and the index function specifies the use to be made of the control word (see below). A transmit instruction causes the transmission of data between peripheral equipment and storage or within storage the data comprising a character or part of word or words taken in succession or at scattered addresses. An arithmetic instruction (Fig. 4) specifies by its operation portion the four arithmetic operations or a compare operation in which a group of characters at an address specified by the control word is compared with a group of characters set up in the registers to produce a result high, low, or equal; the modifier causes such operations as clearing the register in which the result is to be placed, rounding or treating one operand as a positive number; the operand gives the address of one of the operands, the other is given by the control word; the first two places, counting from the left, control define the amount of left shift to be given to a number word of ten characters when entered into the accumulator, or such functions as floating shift or upper accumulator which states that a word is to be placed in the upper accumulator only. Floating shift means that the amount of shift is to be taken from a significant figure indicator which shows the position of the first significant digit numbering from the left. The effect is to normalize the number. Floating shift, store, means that the amount of shift is stored at a fixed address. An indexed shift causes the amount in this fixed address to be added to the amount of shift specified. The units and tens positions of control specify the field of the word to be operated on, the tens position containing the highest order character position of the field and the units position the highest order character position of the next field. The maximum field is ten characters and if the units figure is lower than the tens figure a split field operation is indicated. A branch or jump instruction (Fig. 5) is used to specify tests and consequent conditional or unconditional jumps. The operand portion gives the address of an instruction to be executed should a jump occur. The tests are given by the control portion and may involve index, the relative magnitude of the working address of a control word to that of the end address, balance, which tests the sign or magnitude of the result of the last arithmetic operation, field, which examines the significant length of an information word in relation to the field specified, compare, an operation similar to the arithmetic compare operation, in-out, to test the result of an input-output instruction word with 0 modifier, state, to test the state (as defined above) of the last control word, and the switch tests check the setting of manual switches. The operation portion of the instruction word specifies if a jump is to be made in accordance with a predetermined state of the control word at the index address, and also includes unconditional jump and halt operations. The modifier codes relate to the state of the word at the index address, codes 4 to 7 for example specifying that the test is performed and if satisfied the word is set to a particular state after which the state is tested and the operation, jump or halt, specified by the operation code performed. The immediate cause of a jump is the state of an interrogated word, although the final cause may be a test. A logic instruction provides that all or part of any storage word may be changed for example by means of and, or, or exclusive-or comparisons between the bits of two words. Control words.-These are of three types, each having a two-character condition code, a fourcharacter reset address, a five-character working address and a five-character and address. A control word may be associated with more than one instruction word. The use of a record word is illustrated in Fig. 10, in association with a transmit instruction word. The operand specifies the tape unit from which data is to be read into store. Control specifies the address of the record word of which the working address gives the location in storage of the first data word, and the end address gives the location of the last data word. As each word is read in the working address is advanced by one and the operation stops when the working address of the record word equals the end address. An index word (Fig. 7) is used in conjunction with the index function code of an instruction word. The function code includes four main operations and combinations of them: reset, which causes the contents of the index address of the instruction word to be replaced by the contents of the reset address of the index word; index operand, which causes the working address of the word at the index address of the instruction word to be added to the operand of the instruction word, the sum being used to address storage; advance causes the working address to be incremented by one after each operation; and modify which causes storage to be addressed by the working address of the index word to obtain an operand for the operation specified by the instruction word, the working address is then added to the operand portion of the instruction and the sum replaces the working address. The condition code of an index word includes the condition end, which terminates an operation when the working and end addresses are equal, and reset, which has the same meaning as in the function code. A routine word is used to call in subroutines as a result of a branch operation. It has only two conditions, off and on, and the working address may either (1) provide the storage address of a branch instruction word by indexing the working address of the routine word with the operand of the instruction word being executed as a result of function code index operand, or (2) provide the address of a control word specifying the return address to the next main programme instruction after performance of the sub-routine; the end address may specify the address of a word in which the return address is stored. If this word is an instruction word the return address is in the operand portion, if a control word, in the working address portion. One use of a routine word in association with branch instructions is shown in Fig. 21. Instruction 1066 is a " branch if on " instruction, on referring to the word 0132 specified by the index address. The modifier (4) specifies that word 0132 is set on if the test, zero balance of a number in the accumulator, specified by control is satisfied. Operand gives the address of the first word in the sub-routine. The end address of the routine word specifies the word itself and the working address will contain the return address entered when a branch is made. If a branch is made at instruction 1066, the working address will be 01067. The sub-routine ends at instruction 2512 with an unconditional branch to the address given by adding the operand (0000) of 2512 to the working address

    Improvements in or relating to electronic data processing machines
    6.
    发明专利
    Improvements in or relating to electronic data processing machines 未知

    公开(公告)号：GB1108800A

    公开(公告)日：1968-04-03

    申请号：GB1360665

    申请日：1965-03-31

    Applicant: IBM

    Inventor： AMDAHL GENE MYRON ,  JOHNSON JACOB RAYMOND ,  ROOD JOHN WILLIS ,  CRANEVALE RICHARD JOSEPH ,  UPDIKE BRUCE MARTIN ,  VILLANTE ANTHONY EUGENE ,  BLAAUW GERRIT ANNE ,  WEBER HELMUT ,  CALINGAERT PETER ,  CASE RICHARD PAUL ,  BOEHM ELAINE MARIE ,  HANE WILLIAM PORTER ,  JR CHARLES BERTRAM PERKINS ,  COLLINS ARTHUR FREDERICK ,  GREENE JACK ELLIS ,  MAGDALL ALBERT ALLAN

    IPC: G06F3/00 ,  G06F3/06 ,  G06F3/12 ,  G06F7/38 ,  G06F7/50 ,  G06F7/575 ,  G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/302 ,  G06F9/32 ,  G06F9/46 ,  G06F11/16 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/22 ,  G06F13/26 ,  G06F13/38 ,  G06F15/78 ,  G06F17/21

    Abstract: 1,108,800. Electric digital calculators and data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. 31 March, 1965 [6 April, 1964], No. 13606/65. Headings G4A and G4C. In a data processor, variable-format macroinstructions read from a main memory into selected registers control accessing of a microprogramme read-only store. Data representations-The machine can handle: (a) Fixed-point numbers which are signed binary numbers of one of two lengths. (b) Floating-point numbers (signed) consisting of a " fraction " field of single or double precision length containing binary-coded hexadecimal digits, the fraction field being considered multiplied by 16 raised to the power of a number given in a 7-bit " characteristic " field. (c) Decimal numbers containing a variable number of binary-coded decimal digits, the code 1101 being used to indicate " minus " and the other unused four-bit codes to indicate " plus." Two BCD digits occupy an 8-bit byte in the so-called packed format, or the byte contains one digit plus zone bits in the unpacked (or zoned) format. (d) Logical information in various length fields. Macro-instruction format.-(Figs. 21-25, not shown). Each macro-instruction contains besides an operation code, either (a) the addresses of two operands (RR), or (b) the address of one operand, and two fields which when added give the address of a register containing a number to be added to another field in the instruction to give a second operand address (RX), or (c) two operand addresses and a field to be added to the contents of a register specified by another field in the instruction to give a third operand address (RS), or (d) fields specifying the lengths of two operands, the addresses of two registers and two numbers which when added to the contents of the registers respectively give the addresses of the left-most bytes of the two operands (SS), or (e) one operand (directly) and the address of a register the contents of which are to be added to those of another field in the instruction to get the address of a single-byte second operand (SI). The formats used for different types of operations are as follows: floating-point (RR, RX), fixed-point (RR, RX, RS), decimal (SS), logical (RR, RX, RS, RI, SS). In all macro-instructions, the first two bits of the operation code portion specify the instruction format and length. Programme status words (Fig. 27a, not shown).-One of these words partially controls machine operation at any one time. When operation is interrupted (e.g. for I/O servicing), the current programme status word (PSW) is stored and another is introduced. The PSW has fields to specify: (a) which possible sources of interruption are permitted to cause interruption, (b) storage protection key, (c) whether detection of a machine malfunction is to result in interruption, and execution of diagnostic procedures, (d) whether the CPU is running or waiting, (e) whether the CPU is executing a problem programme or a monitor programme, (f) cause of interruption, (g) length of last instruction executed, (h) condition code, (i) which of four events are to result in interruption, the events being fixed-point overflow, decimal overflow, exponent overflow, and " significance " (i.e. the occurrence of an allzero fraction in the result of a floating-point addition or subtraction), (j) address of next macro-instruction. Possible sources of interruption.-(a) Request for I/O operation. (b) Programme interruption due to programme error. (c) Monitor call. (d) External, e.g. when a timer value is decremented beyond zero, when an operator presses a button or when an external unit (e.g. another CPU) signals on any one of six lines provided. (e) Detection of machine malfunction. A predetermined priority order is provided for simultaneous interrupt attempts. If the storage protection feature is not provided in the computer, detection of a non-zero protection key in the PSW causes an immediate interruption. Manual controls.-These include: (a) A rate switch determining whether the machine will operate continuously on being started, or perfoim one macro-instruction and then stop until restarted. (b) Address keys to address a storage location within a storage area selected by a storage selection switch. (c) Data keys for specifying data to be stored in an addressed location, (d) A button to cause display of information in an addressed location. (e) Address compare switches to set an address on recognition of which the CPU will stop. Read-only storage.-(Figs. 4am, 45a-45c, 46a-46d, not shown).-Two decoders select a driver transistor by signals applied to the base and emitter terminals respectively to read out two words in a capacitive read-only store to sense-amplifiers, the outputs of half the amplifiers being stored in latches under control of a further address bit. By this scheme the number of drivers is halved by doubling the number of amplifiers. Alternatively, each driver may read out four words, the number of amplifiers being twice as large again, and so on. Arithmetic and logic unit and checking. (Figs. 35a-35i, not shown).-The ALU can perform addition or subtraction (binary or decimal) or AND, OR, EXCLUSIVE-OR functions, depending on control signals. Operations are done on the normal and inverted forms of the operands and the results compared to give an error indication if inconsistent. Multiplication.-Binary multiplication is done utilizing tables in which the multiplier is stored in both single and doubled form. Decimal multiplication is done by an algorithm involving successive subtractions followed by multiplicand end digit testing operations and shift of multiplier. Division.-Binary division is by repeated addition or subtraction operations of the divisor to/from the dividend, each followed by shift of the dividend, whether the addition or subtraction operation is used at any time depending on the sign of the result of the last operation. Decimal division is done by repeated subtraction. Other features.-The Specification describes a complete micro-programme-controlled computer in considerable detail, including for instance a complete dictionary of micro-instruction words, and micro-programmes for representative macroinstructions. Also described are details of control of input/output (I/O) operations, editing, branching, memory protection and other features, which are, however, the subject of separate patents.

    7.
    发明专利
    未知

    公开(公告)号：DE1203504B

    公开(公告)日：1965-10-21

    申请号：DEJ0024672

    申请日：1963-11-02

    Applicant: IBM

    Inventor： OTTAWY GERALD HOWARD ,  BOLAND LAWRENCE JOSEPH ,  BLAAUW GERRIT ANNE ,  KESLIN ROBERT

    IPC: G06F7/491 ,  G06F7/52

    Abstract: 1,049,680. Digital computers; division. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 5, 1963 [Nov. 5, 1962], No. 43554/63. Heading G4A. Division is performed by a trial-and-error method. A quotient is guessed and multiplied by the divisor in unit 10 the result being subtracted from the dividend. The quotient is used to address, through circuit 3, a table lookup device which reads out a higher (or equal) and lower quotient for the next try. If there is a carry out of the subtraction unit the higher quotient becomes the next guess, if not the lower quotient is used. The process is continued until the quotients in registers 5 and 6 are one even and one odd. Whichever of these is used is then the required answer and is transferred to register 14. The result of the subtraction is then the remainder and is transferred to the dividend register 1. If the radix is 16 the initial quotient could be 8 and the first pair of quotients selected are 4 and 12. If the radix is 10 the initial quotient could be 4 and the first pair of quotients 2 and 6. The detection of the highest order out-carry can be by means of carry-look-ahead apparatus.

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