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    Data processing apparatus
    4.
    发明专利
    Data processing apparatus 未知

    公开(公告)号：GB1098620A

    公开(公告)日：1968-01-10

    申请号：GB2078166

    申请日：1966-05-11

    Applicant: IBM

    Inventor： KESLIN ROBERT

    IPC: G06F11/10

    Abstract: 1,098,620. Digit-by-digit processing apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 25, 1966 [May 11, 1966], No. 20781/66. Heading G4A. In a data processing apparatus including two input registers A and B each able to accommodate words of four parity checked bytes (each byte comprising 8 data bits and 1 parity bit) and an arithmetic or logical unit having a capacity equal to only four bits (i.e. one decimal digit), means are provided for operating on digits one at a time and for regenerating parity bits at each stage of the operation. As shown (Fig. 1), selected decimal digits from the registers A and B are transferred to the logic connect and carry generator circuits of the A.U. by way of straight-cross circuits 24, 22 (which are associated with parity check circuits 20). The resulting decimal digit together with the unprocessed (C) digit from register B is fed to the output register (of one byte capacity) at the bottom of Fig. 1. Using entirely separate logical circuits, a new parity bit P is generated from the two processed input digits (A and B) and the nonprocessed digit C. The resultant parity checked byte is then returned to register B and the next digits dealt with (by switching straight-cross circuits 24, 22 to the other digit of the same byte or by stepping on to the next byte). Detailed description of the components shown generally in Fig. 1, is given with respect to Figs. 2-13 (not shown). Instead of decimal operations, hexa-decimal (radix 16) or pure binary operations, are possible. Sixteen different logical operations on the input date are provided for, including complement addition and exclusive or.

    5.
    发明专利
    未知

    公开(公告)号：DE1203504B

    公开(公告)日：1965-10-21

    申请号：DEJ0024672

    申请日：1963-11-02

    Applicant: IBM

    Inventor： OTTAWY GERALD HOWARD ,  BOLAND LAWRENCE JOSEPH ,  BLAAUW GERRIT ANNE ,  KESLIN ROBERT

    IPC: G06F7/491 ,  G06F7/52

    Abstract: 1,049,680. Digital computers; division. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 5, 1963 [Nov. 5, 1962], No. 43554/63. Heading G4A. Division is performed by a trial-and-error method. A quotient is guessed and multiplied by the divisor in unit 10 the result being subtracted from the dividend. The quotient is used to address, through circuit 3, a table lookup device which reads out a higher (or equal) and lower quotient for the next try. If there is a carry out of the subtraction unit the higher quotient becomes the next guess, if not the lower quotient is used. The process is continued until the quotients in registers 5 and 6 are one even and one odd. Whichever of these is used is then the required answer and is transferred to register 14. The result of the subtraction is then the remainder and is transferred to the dividend register 1. If the radix is 16 the initial quotient could be 8 and the first pair of quotients selected are 4 and 12. If the radix is 10 the initial quotient could be 4 and the first pair of quotients 2 and 6. The detection of the highest order out-carry can be by means of carry-look-ahead apparatus.

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