中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.019 seconds)

    Integrated memory system with block transfer to a buffer store
    4.
    发明授权
    Integrated memory system with block transfer to a buffer store 失效
    集成存储器系统，具有块传输到缓冲存储器

    公开(公告)号：US3588829A

    公开(公告)日：1971-06-28

    申请号：US3588829D

    申请日：1968-11-14

    Applicant: IBM

    Inventor： BOLAND LAWRENCE J ,  GRANITO GERRY D

    IPC: G06F12/08 ,  G06F13/10 ,  G06F13/16 ,  G06F9/08

    CPC classification number: G06F13/10 ,  G06F12/0859 ,  G06F12/0862 ,  G06F13/1673

    Abstract: A DATA PROCESSING SYSTEM HAS A MEMORY HIERARCHY INCLUDING A HIGH-SPEED LOW-CAPACITY BUFFER STORE (BS) LOCATED BETWEEN A CENTRAL PROCESSING ELEMENT (CPE) AND A LOW SPEED HIGH-CAPACITY MAIN STORE (MS). MEMORY ACCESSING, TO STORE DATA IN OR FETCH DATA FROM AN ADDRESSED WORK LOCATION, BY THE CPE AND BY CHANNELS IS CONTROLLED BY A STORAGE CONTROL UNIT (SCU). ADDRESSES SPECIFIED REFER TO MS WORK LOCATIONS. FOR CPE ACCESS REQUESTS, A TEST IS MADE TO DETEMINED WHETHER THE CONTENT OF THE MS ADDRESSED LOCATION IS RESIDENT IN THE BS. IF IT IS, THEN A STORE IS MADE IN BOTH THE BS AND MS WHILE A FETCH IS MADE ONLY FROM THE BS. IF THE ADDRESSED WORD LOCATION IS NOT RESIDENT IN THE BS, THEN A STORE IS MADE ONLY IN MS AND A FETCH IS MADE FROM THE ADDRESSED LOCATION OF MS. THE DATA FETCHED FROM THE ADDRESSED MS LOCATION IS TRANSFERRED TO THE CPE AND LOADED IN A WORD LOCATION OF THE BS. WHEN SUCH A FETCH IS MADE TO MS, THE SCU ALSO FETCHES ADDITIONAL WORDS, CONTIGUOUS TO THE ADDRESSED WORD, TO FORM A BLOCK AND LOADS THE BLOCK IN THE BS. OVERLAPPING OPERATION ALLOWS A PLURALITY OF BLOCK TRANSFER FROM MS TO BE INITIATED BY THE SCU FOR SUCCESSIVE ACCESS REQUESTS WHICH FIND THE ADDRESSED LOCATIONS NONRESIDENT IN THE BS. CHANNEL REQUESTS ACCESS ONLY THE MS. ASSOCIATED WITH EACH BLOCK OF WORDS IN BS IS A VALID BIT WHICH PERMITS ACCESS TO WORDS IN BS ONLY WHEN SET. DURING A CHANNEL STORE, IF THE ADDRESSED LOCATION IS IN THE BS, THE VALID BIT ASSOCIATED WITH THAT LOCATION IS RESET SIGNIFYING THAT THE DATA CONTENT OF THE CORRESPONDING MS LOCATION HAS BEEN CHANGED.

    NON-SHORTING PIN SYSTEM
    7.
    发明专利
    NON-SHORTING PIN SYSTEM 未知

    公开(公告)号：CA1180403A

    公开(公告)日：1985-01-02

    申请号：CA446264

    申请日：1984-01-27

    Applicant: IBM

    Inventor： BOLAND LAWRENCE J

    IPC: H01R24/00 ,  H01R12/89 ,  H05K1/11 ,  H01R23/70 ,  H01R23/68

    Abstract: Non-Shorting Pin System The invention is a zero insertion force printed circuit board edge connector that ensures electrical connection under a worst-case accumulation of mechanical tolerances while precluding the short circuiting of connector contact pins in the absence of a board within the connector. The contact pins of the connector are formed so that the contact regions of the contact pins lie in at least two horizontal planes. The longer pins located on one side of the connector are located opposite the shorter pins on the other side of the connector. When the connector is actuated in the absence of a printed circuit board, the short pins will move under the opposing long pins but the pins will not short circuit. During actuation, the pins will move more than half way across the connector opening thereby guaranteeing connection to any card regardless of dimensional tolerance or of card position within the connector opening.

Patent Agency Ranking