公开(公告)号：CA1156767A

公开(公告)日：1983-11-08

申请号：CA364528

申请日：1980-11-12

Applicant: IBM

Inventor： BURK JOHN L ,  CORMIER ROGER L ,  HARTUNG MICHAEL H ,  LARNER RAY A ,  LUCAS DONALD J ,  LYNCH KENNETH R ,  MOORE BRIAN B ,  PAGE HOWARD L ,  WANSOR DAVID H ,  ZEITLER CARL JR

IPC: G06F13/00 ,  G06F13/12 ,  G06F15/167 ,  G06F9/00 ,  G06F15/00

Abstract: Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request. An "adapter" processor associated with each host and subsystem operates on an asynchronous basis to transfer messages and data relative to the associated host or subsystem. One or more processing "engines" in each adapter communicates with one or more CPU's in the associated host or subsystem through an associated "adapter store". A portion of each adapter store is used as a buffer pool for constructing "subchannel control spaces" to control transfers of messages and data. Elements of each subchannel control space are returned to free status as soon as they are not needed for sustaining associated transfers. PO9-78-012

公开(公告)号：CA1176379A

公开(公告)日：1984-10-16

申请号：CA403594

申请日：1982-05-21

Applicant: IBM

Inventor： CORMIER ROGER L ,  DUGAN ROBERT J ,  GUYETTE RICHARD R ,  WANISH PAUL J ,  ZEITLER CARL JR

IPC: G06F13/12 ,  G06F13/14 ,  G06F13/40 ,  G06F15/177 ,  H04L69/14 ,  G06F3/04

Abstract: PO9-79-010 METHOD FOR ESTABLISHING VARIABLE PATH GROUP ASSOCIATIONS AND AFFILIATIONS BETWEEN "NON-STATIC" MP SYSTEMS AND SHARED DEVICES Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Related path state indications are stored peripherally in path map tables and define path group associations for sustaining path-independent I/O operations. When a device is reserved via one path in a path group the reserve affiliation is extended automatically (in the path tables) to each path in the group, thereby rendering each path accessible in a reserved mode. The path defining commands are used for adding paths to, resigning paths from and disbanding groups. Special sensing commands axe used for sensing path reservation and grouping states. When a command for adding or resigning a path is presented to a reserved device via one path in a group the reserve is automatically realigned to the enlarged or reduced group. When a command for disbanding a group is presented to a reserved device the reserve is realigned to apply only to the path on which the command is presented. The foregoing special commands are required to be obeyed by the device even if it currently has a conflicting allegiance to the same system or another system. Consequently, paths can be added to an established path group without requiring potentially premature release of any allegiance.

公开(公告)号：CA773734A

公开(公告)日：1967-12-12

申请号：CA773734D

Applicant: IBM

Inventor： BOLAND LAWRENCE J ,  ZEITLER CARL JR

公开(公告)号：CA1175573A

公开(公告)日：1984-10-02

申请号：CA413263

申请日：1982-10-12

Applicant: IBM

Inventor： CORMIER ROGER L ,  DUGAN ROBERT J ,  GUYETTE RICHARD R ,  HANKISON RONALD L ,  HAO MING C ,  LEVIN ARTHUR L ,  MCCLAIN GEORGE A ,  WANISH PAUL J ,  ZEITLER CARL JR

IPC: G06F3/00 ,  G06F11/34 ,  G06F9/00 ,  G06F15/00

Abstract: P09-78-018 METHOD AND APPARATUS FOR MEASUREMENTS OF CHANNEL OPERATION A channel for a data processing system is provided with a time of day clock that is synchronized with the time of day clock of the associated central processor. Both the central processor and the channel processor record times of particular events, and the channel uses these times to calculate two times called Function Pending and Function Active. Both times begin when the central processor executes an instruction to begin an I/O operation. Function Pending ends when the channel has made successful initial selection. This time shows delays by the channel processor in scheduling the channel resources for I/O operations. Function Active ends at Channel End. A new instruction, Set Channel Monitor, enables or disables these measurements. An information block for each subchannel defines one of several measurement modes for a subchannel or disables the subchannel from measurement.

公开(公告)号：CA1143852A

公开(公告)日：1983-03-29

申请号：CA360340

申请日：1980-09-16

Applicant: IBM

Inventor： CHRISTENSEN NEAL T ,  VAN LOO WILLIAM C ,  WERNER ROBERT H ,  WETZEL JOSEPH A ,  ZEITLER CARL JR

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16 ,  G06F15/177

Abstract: MULTIPROCESSOR MECHANISM FOR HANDLING CHANNEL INTERRUPTS The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program. An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty. A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs. In each CP, acceptance determining circuits connect to the broadcast bus and accept the highest-priority-unmask nonempty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state. Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queu at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP. An inhibit register in the interrupt controller in the SC inhibits selected bits on the broadcast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends it acceptance of the P09-79-011 corresponding queue, so that any CP can select the next entry on the corresponding queue. When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state. PO9-79-011