公开(公告)号：AT477588T

公开(公告)日：2010-08-15

申请号：AT05808156

申请日：2005-11-16

Applicant: IBM

Inventor： BURRELL LLOYD ,  CHEN HOWARD ,  HSU LOUIS ,  SAUTER WOLFGANG

IPC: H01L21/48 ,  H01L23/14 ,  H01L23/538

Abstract: Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

公开(公告)号：DE602005022919D1

公开(公告)日：2010-09-23

申请号：DE602005022919

申请日：2005-11-16

Applicant: IBM

Inventor： BURRELL LLOYD ,  CHEN HOWARD HAO ,  HSU LOUIS ,  SAUTER WOLFGANG

IPC: H01L21/52 ,  H01L23/14 ,  H01L23/538