公开(公告)号：JP2007306008A

公开(公告)日：2007-11-22

申请号：JP2007141486

申请日：2007-05-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CYRILLE CABRAL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS ,  WONG KEITH KWONG HON

IPC: H01L21/8242 ,  C23C14/00 ,  C23C14/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/318 ,  H01L27/108

CPC classification number: H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

Abstract: PROBLEM TO BE SOLVED: To provide the method of forming a capacitor on an original position in a semiconductor structure.
SOLUTION: First, a previously-treated semiconductor substrate is positioned in a sputtering chamber. Then, Ar gas is flown into the sputtering chamber and a first heat-resistant metal-silicon-nitrogen layer is adhered in a sputtering manner onto the substrate from the target of heat-resistant metal silicide or two targets of heat-resistant metal and silicon. Then, N
2 gas is flown into the sputtering chamber until the density of N
2 gas in the chamber reaches at least 35%, and a second heat-resistant metal-silicon-nitrogen layer is adhered in the sputtering manner onto the first heat-resistant metal-silicon-nitrogen layer. Then, the flow of N
2 gas is stopped and a third heat-resistant metal-silicon-nitrogen layer is adhered in the sputtering manner onto the second heat-resistant metal-silicon-nitrogen layer. Then, the multilayer stack of heat-resistant metal-silicon-nitrogen is formed on the capacitor using photolithography.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供在半导体结构中的原始位置形成电容器的方法。 解决方案：首先，将预先处理的半导体衬底放置在溅射室中。 然后，将Ar气体流入溅射室，并且将第一耐热金属硅 - 氮层从耐热金属硅化物的靶或两个耐热金属和硅的靶以溅射方式附着到基板上 。 然后，将N 2 气体流入溅射室，直到室内的N 2 SB 2气体的密度达到至少35％，而第二耐热金属硅 - 氮层以溅射方式粘附到第一耐热金属 - 硅 - 氮层上。 然后，停止N SB 2气体的流动，并且以溅射方式将第三耐热金属 - 硅 - 氮层粘附到第二耐热金属 - 硅 - 氮层上。 然后，使用光刻法在电容器上形成多层叠层的耐热金属硅 - 氮。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003060084A

公开(公告)日：2003-02-28

申请号：JP2002149960

申请日：2002-05-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CYRILLE CABRAL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS ,  WONG KEITH KWONG HON

IPC: C23C14/00 ,  C23C14/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a capacitor at a source position inside a semiconductor structure.
SOLUTION: In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to deposit by sputtering a first refractory metal-silicon-nitrogen layer 14 on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N
2 gas is then flown into the sputtering chamber until that the concentration of N
2 gas in the camber is at least 35% to deposit by sputtering a second refractory metal-silicon-nitrogen layer 16 on top of the first refractory metal-silicon-nitrogen layer. The N
2 gas flow is then stopped to deposit by sputtering a third refractory metal-silicon-nitrogen layer 18 on top of the second refractory metal-silicon-nitrogen layer. The multi- layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into the capacitor.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种在半导体结构内的源极位置形成电容器的方法。 解决方案：在该方法中，首先将预处理的半导体衬底放置在溅射室中。 然后通过从难熔金属硅化物靶或从难熔金属和硅的两个靶溅射基底上的第一难熔金属硅 - 氮层14，将Ar气体流入溅射室中。 然后将N 2气体流入溅射室，直到通过在第一耐火金属 - 硅 - 氮层的顶部溅射第二难熔金属 - 硅 - 氮层16来沉积外弧中的N 2气体的浓度至少为35％ 。 然后通过在第二难熔金属 - 硅 - 氮层的顶部溅射第三耐火金属 - 硅 - 氮层18来停止N2气流以沉积。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：JP2003007062A

公开(公告)日：2003-01-10

申请号：JP2002182086

申请日：2002-06-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： HSU LOUIS ,  RIIKON WAN

IPC: G11C11/408 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C8/12 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/4076

Abstract: PROBLEM TO BE SOLVED: To provide a decoding system for performing a plurality of pieces of operation for the semiconductor memory device of a stack bank type.
SOLUTION: A decoding unit is provided to a memory bank group provided with a plurality of memory banks. When a reading and writing bank address coincides with two different memory banks in the same memory bank group, the decoding unit receives a reading and writing address and generates two different row selection signals for reading and writing operation in the two different banks. Based on the row selection signal, row decoder units in the two coincident banks simultaneously activate a target row designated by the reading and writing address.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于对堆叠类型的半导体存储器件执行多个操作的解码系统。 解决方案：解码单元提供给设置有多个存储体的存储体组。 当读取和写入存储体地址与同一存储体组中的两个不同的存储体一致时，解码单元接收读取和写入地址，并在两个不同的存储体中产生用于读取和写入操作的两个不同的行选择信号。 基于行选择信号，两个重合行中的行解码器单元同时激活由读取和写入地址指定的目标行。

公开(公告)号：WO0137320A3

公开(公告)日：2001-12-06

申请号：PCT/US0030404

申请日：2000-11-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： REITH ARMIN M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

IPC: G06F17/50 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

Abstract translation: 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

公开(公告)号：WO0195382A3

公开(公告)日：2002-08-29

申请号：PCT/US0118539

申请日：2001-06-07

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L21/76 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L21/31053 ,  H01L21/28525 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684

Abstract: A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography. In the polishing process, the diamond or diamond-like carbon polish-stop layer and any remaining protective layer are used as polish-stop layers. The diamond or diamond-like carbon polish-stop layer allows for an improved planar surface, thereby resulting in an sufficient decrease in topography at the surface of the inter-level dielectric.

Abstract translation: 使用金刚石或类金刚石碳层作为抛光停止件的方法，其使用镶嵌工艺流程将金属层图案化成层间电介质基板。 在图案化金属层之前，将金刚石或类金刚石碳层沉积在基板的表面上。 然后将保护层沉积在金刚石或类金刚石碳抛光层上，其中这种保护层可以用作另外的抛光停止层。 一起使用金刚石或类金刚石碳抛光层和保护层作为用于图案化将成为金属特征的沟槽的硬掩模，其中这种保护层保护金刚石或类金刚石碳抛光 在图案化过程中。 在沉积导电金属层之后，电介质基底被抛光以除去过量的导电材料以及形貌。 在抛光过程中，将金刚石或类金刚石碳抛光层和任何剩余的保护层用作抛光 - 停止层。 金刚石或类金刚石碳抛光层允许改进的平面表面，从而导致层间电介质表面的形貌的充分降低。

公开(公告)号：WO02058072A3

公开(公告)日：2002-09-26

申请号：PCT/US0201406

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HSU LOUIS ,  FRANKOWSKY GERD ,  WEINFURTNER OLIVER

IPC: G11C11/407 ,  G06F15/78 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406

CPC classification number: G11C11/406 ,  G11C2207/104 ,  G11C2207/2254

Abstract: A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the refresh cycle time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.

Abstract translation: 一种新颖的DRAM刷新方法和系统以及设计低功耗漏电监测装置的新方法。 利用DRAM刷新方法，基于单元泄漏条件来调整刷新周期时间。 设计低功率泄漏监测装置的方法使用与真实阵列中的单元相同的存储单元。 该监视器单元被设计成它将代表平均单元或最坏的单元泄漏状况。 如果泄漏严重，则刷新周期时间会显着减少或减半。 如果泄漏电平非常低或不可检测，则刷新周期时间显着增加或加倍。 如果泄漏中等或在正常范围内，则刷新时间被优化，使得用于DRAM刷新的功耗最小化。 该方法优于现有方法，即基于芯片温度调整刷新周期时间的优点包括：（1）考虑到非温度依赖性泄漏因素的贡献，（2）本发明不需要不同的 处理步骤或额外的处理成本，以及（3）本发明是一种直接的方法，监测单元不需要任何校准。 此外，其泄漏机制和可靠性问题与实际阵列中的单元格完全相同。

公开(公告)号：WO0214886A3

公开(公告)日：2002-07-11

申请号：PCT/US0123168

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEHMANN GUNTHER ,  FRANKOWSKY GERD ,  HSU LOUIS ,  REITH ARMIN

IPC: G01R31/3183 ,  G01R31/319 ,  G11C29/10 ,  G11C29/56 ,  G11C29/00

CPC classification number: G11C29/10 ,  G01R31/3183 ,  G01R31/31926 ,  G11C29/56

Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes the backwards transformation from a given set of logical data pattern. Since the method is automatic, no knowledge of the data scrambling inside the memory circuit is required.

Abstract translation: 用于在存储器电路中生成逻辑硬件测试模式的自动方法基于给定的物理模式。 该方法包括从给定的一组逻辑数据模式向后转换。 由于该方法是自动的，因此不需要知道存储器电路内的数据加扰。

公开(公告)号：AT548756T

公开(公告)日：2012-03-15

申请号：AT05807945

申请日：2005-11-03

Applicant: IBM

Inventor： CHEN HOWARD ,  HSU LOUIS

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/18 ,  H01L29/06

Abstract: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.

公开(公告)号：AT441938T

公开(公告)日：2009-09-15

申请号：AT06830385

申请日：2006-12-05

Applicant: IBM

Inventor： MANDELMAN JACK ,  CHENG KANGGUO ,  HSU LOUIS ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/78

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

公开(公告)号：DE602005022919D1

公开(公告)日：2010-09-23

申请号：DE602005022919

申请日：2005-11-16

Applicant: IBM

Inventor： BURRELL LLOYD ,  CHEN HOWARD HAO ,  HSU LOUIS ,  SAUTER WOLFGANG

IPC: H01L21/52 ,  H01L23/14 ,  H01L23/538