公开(公告)号：JP2004128494A

公开(公告)日：2004-04-22

申请号：JP2003325279

申请日：2003-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BYONJU PAKU ,  MANDELMAN JACK A ,  FURUKAWA TOSHIHARU

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

Abstract: PROBLEM TO BE SOLVED: To provide a multi-mesa FET structure having a doped sidewall for a source/drain region and its forming method. SOLUTION: This method makes use of the fact that when using a doping method which does not depend on a geometric shape such as a vapor doping or a plasma doping, a uniform doping of the whole sidewall is obtained by exposing the source and the drain sidewall during manufacturing. As a result, a device manufactured can have a large quantity of current per unit area of a silicon because it has a threshold voltage and a current density that does not depend on the depth and controlled with accuracy, and also its mesa quantity is extremely high compared with a mesa which can be formed by a conventional technology. Instead of a normal subtractive etching method, a multi-mesa FET structure forming method using a Damascene method gate process or a Damascene method alternate gate process is included. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001332602A

公开(公告)日：2001-11-30

申请号：JP2001073029

申请日：2001-03-14

Applicant: IBM

Inventor： BALLANTINE ARNE W ,  PETER A EMI ,  WALTER J FREY ,  MICHAEL J GYANBERO ,  NINA GAG ,  BYONJU PAKU ,  DONALD L WILSON

IPC: B65G49/00 ,  B65G49/07 ,  C23C16/44 ,  C23C16/54 ,  H01L21/00 ,  H01L21/205 ,  H01L21/677 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and a method for controlling the wafer temperature and environment. SOLUTION: The apparatus 10 of this inventive comprises an RTP chamber (20) having an inert or reducing environment. The RTP chamber (20) contains a pedestal 24 for holding a single wafer 16, and a heater unit 22 disposed to heat the single wafer uniformly at a high rate. The apparatus 10 further comprises a cooling chamber 30 having a reducing or inert environment and disposed contiguously to the RTP chamber to open selectively thereto, a first loading chamber 40 having an inert or reducing environment and containing a cassette 44 for holding one or a plurality of wafers, and a heat treatment chamber 50, e.g. an LPCVD furnace, disposed to execute heat treatment of a wafer in the cassette. Wafer handlers 80-83 for carrying a wafer is subjected to temperature control.