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    OXIDATION OF SILICON NITRIDE FILMS IN SEMICONDUCTOR DEVICES
    1.
    发明申请
    OXIDATION OF SILICON NITRIDE FILMS IN SEMICONDUCTOR DEVICES 审中-公开
    在半导体器件中氧化氮化硅膜

    公开(公告)号：WO02099866A3

    公开(公告)日：2003-08-28

    申请号：PCT/EP0206916

    申请日：2002-06-04

    Applicant: IBM ,  COMPANIE IBM FRANCE

    Inventor： BALLANTINE ARNE W ,  FALTERMEIER JONATHAN E ,  FLAITZ PHILIP L ,  GILBERT JEFFREY D ,  GLUSCHENKOV OLEG ,  HEENAN CAROL J ,  JAMMY RAJARAO

    IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/321 ,  H01L21/334 ,  H01L21/8234 ,  H01L29/51

    CPC classification number: H01L21/28202 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66181

    Abstract: Disclosed is a method to convert a stable silicon nitride film (101)covering a silicon substrate (100) into a stable silicon oxide film (102) with a low content of residual nitrogen in the resulting silicon oxide film. This is achieved by performing the steps of (i)providing a low pressure environment for the silicon nitride fim of between about l.33 X10 Pa(100 Torr) to about 13.3 Pa (0.1 Torr);(ii)introducing hydrogen and oxygen into said low pressure environment; and iii maintaining said low pressure environment at a temperature of about 600°C to about 1200 C° for a predetermined amount of time. This is an unexpectedand unique property of the in situ steam generation process since both silicon nitride and silicon oxide materials are chemically very stable compounds. Application of the claimed method to the art of microelectronic device fabrication, such as fabrication of on-chip dielectric capacitors and metal insulator semiconductor field effect transistors, is also disclosed.

    Abstract translation: 公开了一种将覆盖硅衬底（100）的稳定氮化硅膜（101）转换成所得氧化硅膜中残留氮含量低的稳定氧化硅膜（102）的方法。 这通过以下步骤来实现：（i）为约13.3×10 4 Pa（100托）至约13.3Pa（0.1托）的氮化硅膜提供低压环境;（ii）引入氢 和氧气进入所述低压环境; 以及iii将所述低压环境保持在约600℃至约1200℃的温度下一段预定的时间。 这是原位蒸汽产生过程的意想不到的独特性质，因为氮化硅和氧化硅材料都是化学上非常稳定的化合物。 还公开了所要求保护的方法应用于微电子器件制造领域，例如制造片上电介质电容器和金属绝缘体半导体场效应晶体管。

    Feol capacitor and its manufacturing method
    3.
    发明专利
    Feol capacitor and its manufacturing method 审中-公开
    FEOL电容器及其制造方法

    公开(公告)号：JP2003051549A

    公开(公告)日：2003-02-21

    申请号：JP2002162321

    申请日：2002-06-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： BALLANTINE ARNE W ,  BUCHANAN DOUGLAS A ,  CARTIER EDUARD A ,  COOLBAUGH DOUGLAS D ,  GOUSEV EVGENI P ,  OKORN-SCHMIDT HARALD F

    IPC: H01L29/73 ,  H01L21/02 ,  H01L21/28 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/51 ,  H01L29/94

    CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

    Abstract: PROBLEM TO BE SOLVED: To provide an FEOL capacitor such as a polysilicon-polysilicon capacitor and an MIS capacitor wherein high permittivity (high-k) dielectrics whose permittivity k is higher than about 8 can be assembled in a capacitor structure, and a method for manufacturing the FEOL capacitor.
    SOLUTION: First, a lower electrode 12 is formed in an Si containing substrate 10 by using ion implantation. The high permittivity dielectrics 14 whose permittivity k is higher than about 8 is formed on at least a part of the lower electrode 12. A doped Si containing electrode 16 of a bipolar device constituted of an intrinsic base polysilicon layer is formed on the high permittivity dielectrics 14. By performing the above processes, an MIS capacitor can be obtained. By the method, the FEOL capacitor wherein the upper and the lower electrode in which series resistance is small are formed, capacitance per unit area is large, and high frequency response characteristic is superior can be obtained. Further, chip size can be reduced remarkably, and especially in the use of an analog signal and a mixed signal in which a capacitor of large area is used, chip size can be reduced remarkably.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：为了提供诸如多晶硅 - 多晶硅电容器和MIS电容器的FEOL电容器，其电容率k高于约8的高介电常数（高k）电介质可以组装在电容器结构中，以及用于 制造FEOL电容。 解决方案：首先，通过使用离子注入在含Si衬底10中形成下电极12。 介电常数k大于约8的高介电常数电介质14形成在下电极12的至少一部分上。由高介电常数电介质形成由本征基极多晶硅层构成的双极器件的掺杂Si含电极16 通过执行上述处理，可以获得MIS电容器。 通过该方法，形成其中串联电阻小的上电极和下电极的FEOL电容器，每单位面积的电容量大，并且可以获得高的频率响应特性。 此外，芯片尺寸可以显着降低，特别是在使用大面积的电容器的模拟信号和混合信号的使用中，芯片尺寸可以显着降低。

    DUAL/WRAP-AROUND GATE FIELD EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD
    4.
    发明专利
    DUAL/WRAP-AROUND GATE FIELD EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2002043581A

    公开(公告)日：2002-02-08

    申请号：JP2001154502

    申请日：2001-05-23

    Applicant: IBM

    Inventor： JAMES W ADKISSON ,  PAUL D ANGELO ,  BALLANTINE ARNE W ,  CHRISTOPHER S PUTNAM ,  RANKIN JED H

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a dual/wrap-around gate field effect transistor particularly having a short gage length, a low off current and good performance and a method for manufacturing the same. SOLUTION: In the field effect transistor comprising gates each having a length of 10 nm or less and a conductive channel having a width maintained at 1/2 to 1/4 of the length of the gate so that the gates are disposed at least at two sides of the channel, a device having a complete depletion layer is formed without considering the off current. The above-mentioned channel is obtained by forming a groove in a minimum lithographic size, forming sidewalls in the groove and etching a gate structure in a self-alignment manner with the sidewalls. The channel is thereafter epitaxially grown from a source structure in the groove so that the source, the channel and a drain region are integrated in a single crystal structure.

    APPARATUS AND METHOD FOR FORMING A BATTERY IN AN INTEGRATED CIRCUIT
    9.
    发明专利
    APPARATUS AND METHOD FOR FORMING A BATTERY IN AN INTEGRATED CIRCUIT 未知

    公开(公告)号：MY127563A

    公开(公告)日：2006-12-29

    申请号：MYPI20020088

    申请日：2002-01-11

    Applicant: IBM

    Inventor： BALLANTINE ARNE W ,  GROVES ROBERT A ,  LUND JENNIFER L ,  NAKOS JAMES S ,  RICE MICHAEL B ,  STAMPER ANTHONY K

    IPC: H01L21/768 ,  H01L29/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/822 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

    Abstract: A METHOD AND STURCTURE THAT PROVIDES A BATTERY (420) WITHIN AN INTEGRATED CIRCUIT (400) FOR PROVIDING VOLTAGE TO LOW-CURRENT ELECTRONIC DEVICES (900) THAT EXIST WITHIN THE INTERGRATED CIRCUIT. THE METHOD INCLUDES FRONT-END-OF-LINE (FEOL) PROCESSING FOR GENERATING A LAYER OF ELECTRONIC DEVICES ON A SEMICONDUCTOR WAFER (402), FOLLOWED BY BACK-END-OF-LINE(BEOL) INTEGRATION FOR WIRES THE BEOL INTEGRATION INCLUDES FORMING A MULTILAYERED STRUCTURE OF WIRING LEVELS ON THE LAYER OF ELECTORINC DEVICES. EACH WIRING LEVEL INCLUDES CONDUCTIVE METALLIZATION (E.G., METAL-PLATED VIAS CONDUCTIVE WIRING LINES, ETC) EMBEDDED IN INSULATIVE MATERIAL. THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS, AND THE CONDUCTIVE METALLIZATION (432,434,442,444)(E.G.,METAL-PALTED VIAS,CONDUCTIVE WIRING LINES, ETC.)EMBEDDED IN INSULATIVE MATERIAL.THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS,AND THE CONDUCTIVE METALLIZATION CONDUCTIVELY COUPLE POSITIVE (424) AND NEGATIVE (422) TERMINALS OF THE BATERRY TO THE ELECTRONIC DEVICES.THE BATERRY MAY HAVE SEVERAL DIFFERENT TOPOLOGIES RELATIVE TO THE STRUCTURAL AND GEOMETRICAL RELATIONSHIPS AMONG THE BATERRY ELECTRODES AND ELECTROLYTE.MULTIPLE BATTERIES MAY BE FORMED WITHIN ONE OR MORE WIRING LEVELS,AND MAY BE CONDUCTIVELY COUPLE TO THE ELECTRONIC DEVICES.THE MULTIPLE BATERIES MAY BE CONNECTED IN SERIES OR IN PARALLEL.(FIG.1)

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