公开(公告)号：EP1977446A4

公开(公告)日：2009-09-23

申请号：EP07710062

申请日：2007-01-11

Applicant: IBM

Inventor： ANDERSON BRENT A ,  CHAN VICTOR W C ,  NOWAK EDWARD J

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

公开(公告)号：WO2007082266A3

公开(公告)日：2007-12-06

申请号：PCT/US2007060390

申请日：2007-01-11

Applicant: IBM ,  ANDERSON BRENT A ,  CHAN VICTOR W C ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  CHAN VICTOR W C ,  NOWAK EDWARD J

IPC: H01L21/76

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A semiconductor transistor (100) with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor (100) with an expanded top portion of a gate includes (a) a semiconductor region (110)which includes a channel region and first and second source/drain regions (840 and 850); the channel region is disposed between the first and second source/drain regions (840 and 850), (b) a gate dielectric region (411) in direct physical contact with the channel region, and (c) a gate electrode region (510) which includes a top portion (512) and a bottom portion (515). The bottom portion (515) is in direct physical contact with the gate dielectric region (411). A first width (517) of the top portion (512) is greater than a second width (516) of the bottom portion (515). The gate electrode region (510) is electrically insulated from the channel region by the gate dielectric region (411).

Abstract translation: 一种具有扩大的栅极顶部的半导体晶体管（100）及其形成方法。 具有扩展的栅极顶部部分的半导体晶体管（100）包括：（a）包括沟道区以及第一和第二源极/漏极区（840和850）的半导体区（110）; 沟道区设置在第一和第二源极/漏极区（840和850）之间，（b）与沟道区直接物理接触的栅极介电区（411），以及（c）栅电极区（510） 其包括顶部（512）和底部（515）。 底部（515）与栅极电介质区域（411）直接物理接触。 顶部（512）的第一宽度（517）大于底部（515）的第二宽度（516）。 栅极电极区域（510）通过栅极电介质区域（411）与沟道区域电绝缘。

公开(公告)号：SG144775A1

公开(公告)日：2008-08-28

申请号：SG2007006893

申请日：2007-02-02

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHAN VICTOR W C ,  YANG HAINING S ,  LEE YONG MENG ,  LIM ENG HUA

Abstract: DUAL-HYBRID LINER FORMATION WITHOUT EXPOSING SILICIDE LAYER TO PHOTORESIST STRIPPING CHEMICALS Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer (68) is protected from photoresist stripping chemicals by using a hard mask (110) as a pattern during etching, rather than using a photoresist. The hard mask (110) prevents exposure of a silicide layer (68) to photoresist stripping chemicals and provides very good lateral dimension control such that the two nitride liners are well aligned.

公开(公告)号：SG146549A1

公开(公告)日：2008-10-30

申请号：SG2008019333

申请日：2008-03-10

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHAN VICTOR W C ,  SUNFEI FANG ,  DYER THOMAS W ,  LI JINGHONG H ,  JIANG YAN ,  UTOMO HENRY K ,  JUNG TANG TECK

Abstract: SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET Methods of forming a silicide in an embedded silicon germanium (eSiGe) source/drain region using a silicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen- containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.

公开(公告)号：SG139657A1

公开(公告)日：2008-02-29

申请号：SG2007051733

申请日：2007-07-17

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LEE YONG MENG ,  YANG HAINING S ,  CHAN VICTOR W C ,  LIM ENG HUA

Abstract: STRUCTURE AND METHOD TO IMPLEMENT DUAL STRESSOR LAYERS WITH IMPROVED SILICIDE CONTROL An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate (10) with a first device region (12) and a second device region (14). We provide a first type FET transistor (48) in the first device region (12) and provide a second type FET transistor (46) in the second device region (14). We form an etch stop layer (65) over the first and second device regions (12, 14) and forming a first stressor layer (66) over the first device region (12). The first stressor layer (66) puts a first type stress on the substrate (10) in the first device region (12). We form a second stressor layer (71) over the second device region (14). The second stressor layer (71) puts a second type stress on the substrate (10) in the second device region (14). Another example embodiment is the structure of a dual stress layer device having an etch stop layer. Fig. 4.