公开(公告)号：US6432829B2

公开(公告)日：2002-08-13

申请号：US80147301

申请日：2001-03-08

Applicant: IBM

Inventor： MULLER K PAUL L ,  NOWAK EDWARD J ,  WONG HON-SUM P

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/302

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78636 ,  H01L29/78654

Abstract: An improved fin device used as the body of a field effect transistor ("FET") and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor ("MOS") FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.

Abstract translation: 用作场效应晶体管（“FET”）的主体的改进的鳍装置以及制造鳍片装置的改进方法。 翅片器件允许制造尺寸范围为微米至纳米的非常小尺寸的金属氧化物半导体（“MOS”）FET，同时避免通常与这些尺寸的MOSFET相关的典型的短沟道效应。 因此，可以制造更高密度的MOSFET，使得可以在单个半导体晶片上放置更多的器件。 制造翅片装置的过程导致改进的完全平坦化的装置。

公开(公告)号：JP2007134721A

公开(公告)日：2007-05-31

申请号：JP2006304611

申请日：2006-11-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NOWAK EDWARD J ,  CHEN JIA

IPC: H01L29/786

CPC classification number: H01L51/055 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/94

Abstract: PROBLEM TO BE SOLVED: To provide a stable p-type CNTFET and a stable n-type CNTFET by disclosing a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs.
SOLUTION: In order to overcome the ambipolar properties of a CNTFET, source/drain gates 125 are introduced below a CNT 110 opposite source/drain electrodes 105. In this case, the source/drain gates 125 are used to apply either a positive or negative voltage to the ends of a CNT 111 so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. In addition, a complementary CNT can be incorporated into a device by two adjacent CNTFETs configured such that one is an n-type CNTFET and the other is a p-type CNTFET.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过公开克服CNTFET的固有双极性质的CNT技术来提供稳定的p型CNTFET和稳定的n型CNTFET。 解决方案：为了克服CNTFET的双极性，源极/漏极栅极125被引入CNT 110相对的源极/漏极105的下方。在这种情况下，源极/漏极门125用于施加 正电压或负电压到CNT 111的端部，以便将相应的FET分别构造为n型或p型CNTFET。 此外，互补的CNT可以通过配置成使得一个是n型CNTFET并且另一个是p型CNTFET的两个相邻的CNTFET被并入到器件中。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007142417A

公开(公告)日：2007-06-07

申请号：JP2006308667

申请日：2006-11-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  BRENT A ANDERSON ,  JEFFREY B JOHNSON

IPC: H01L21/336 ,  H01L21/283 ,  H01L29/41 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a trigate field effect transistor provided with a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. SOLUTION: Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate dielectric to optimize conductivity in the channel corners. To further emphasize the electric current in the channel corners, the source/drain regions can be formed only in the upper corners of the semiconductor body. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有鳍状半导体本体的三端场效应晶体管，沟道区域和沟道区两侧的源极/漏极区域。 解决方案：厚栅极电介质层将沟道区域的顶表面和相对侧壁与栅极导体分离，以抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极电介质分离，以优化沟道角中的导电性。 为了进一步强调通道角中的电流，源极/漏极区域只能形成在半导体本体的上角处。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：EP1690294A4

公开(公告)日：2010-09-22

申请号：EP04810448

申请日：2004-11-05

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66795

公开(公告)号：EP1908111A4

公开(公告)日：2008-09-03

申请号：EP06788064

申请日：2006-07-21

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BREITWISCH MATTHEW J ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L29/12 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate (101 ); a silicon germanium (SiGe) layer (103) over the substrate (103); a semiconductor layer (105) over and adjacent to the SiGe layer (103); an insulating layer (109a) adjacent to the substrate (101), the SiGe layer (103), and the semiconductor layer (105); a pair of first gate structures (111) adjacent to the insulating layer (1 09a); and a second gate structure (113) over the insulating layer (109a). Preferably, the insulating layer (109a) is adjacent to a side surface of the SiGe layer (103) and an upper surface of the semiconductor layer (105), a lower surface of the semiconductor layer (105), and a side surface of the semiconductor layer (105). Preferably, the SiGe layer (103) comprises carbon. Preferably, the pair of first gate structures (111) are substantially transverse to the second gate structure (113). Additionally, the pair of first gate structures (111) are preferably encapsulated by the insulating layer (109a).

Abstract translation: 一种场效应晶体管（FET）及其形成方法，包括衬底（101）; 在衬底（103）上的硅锗（SiGe）层（103）; 在所述SiGe层（103）上方并且与所述SiGe层（103）相邻的半导体层（105）; 与衬底（101），SiGe层（103）和半导体层（105）相邻的绝缘层（109a）; 一对第一栅极结构（111），与绝缘层（109a）相邻; 和在绝缘层（109a）上的第二栅极结构（113）。 优选地，绝缘层（109a）与SiGe层（103）的侧表面和半导体层（105）的上表面，半导体层（105）的下表面以及半导体层 半导体层（105）。 优选地，SiGe层（103）包含碳。 优选地，该对第一栅极结构（111）基本上横向于第二栅极结构（113）。 此外，一对第一栅极结构（111）优选由绝缘层（109a）封装。

公开(公告)号：EP1488462A4

公开(公告)日：2008-04-23

申请号：EP03719421

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A structure for a transistor that includes an insulator (10) and a silicon structure on the insulator. The silicon structure includes a central portion (155) and Fins (250) extending from ends of the central portion. A first gate (50) is positioned on a first side of the central portion of the silicon structure. A strain-producing layer (11) could be between the first gate (50) and the first side of the central portion (155) of the silicon structure and a second gate (160) is on a second side of the central portion (155) of the silicon structure.

公开(公告)号：EP1573804A4

公开(公告)日：2006-03-08

申请号：EP02798557

申请日：2002-12-19

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/84 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66795

Abstract: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124) , and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.

公开(公告)号：JP2005217418A

公开(公告)日：2005-08-11

申请号：JP2005021176

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/66803

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a fin-type field-effect transistor (FinFET) having an embedded oxide layer 130 on a substrate 110, at least one-layer first structure 112 on the embedded oxide layer and at least one-layer second fin structure 114 on the embedded oxide layer and a manufacturing method of the same. SOLUTION: A first spacer 120 is adjacent to the fin structure 112, and a second spacer 118 is adjacent to the second fin structure 114. The area that the first spacer covers the first fin structure is wider than the area that the second spacer covers the second fin structure. As long as a fin has a wider spacer, a relatively narrow semiconductor doping area 113 is given, and as long as the fin has a narrower spacer, a relatively broader semiconductor doping area 115 is given. Therefore, a difference in doping between the first fin and the second fin takes place depending upon the spacers of different dimensions. The effective width of the second fin varies with the difference in doping between the first fin and the second fin as compared to the first fin. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供在衬底110上具有嵌入氧化物层130的鳍式场效应晶体管（FinFET）的结构，在嵌入的氧化物层上的至少一层第一结构112和 在嵌入的氧化物层上的至少一层的第二鳍结构体114及其制造方法。 解决方案：第一间隔件120邻近翅片结构112，第二间隔件118与第二翅片结构114相邻。第一间隔件覆盖第一翅片结构的区域比第二间隔件118的区域宽 间隔件覆盖第二鳍结构。 只要翅片具有更宽的间隔物，就给出相对较窄的半导体掺杂区域113，并且只要鳍片具有较窄的间隔物，就给出相对较宽的半导体掺杂区域115。 因此，根据不同尺寸的间隔物，发生第一鳍片和第二鳍片之间的掺杂差异。 与第一鳍片相比，第二鳍片的有效宽度随着第一鳍片和第二鳍片之间的掺杂差异而变化。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003008428A

公开(公告)日：2003-01-10

申请号：JP2002116448

申请日：2002-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BRYANT ANDRES ,  COTTRELL PETER EDWIN ,  ELLIS-MONAGHAN JOHN JOSEPH ,  KETCHEN MARK B ,  NOWAK EDWARD J

IPC: H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/094

CPC classification number: G05F3/205 ,  H01L27/0218

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for biasing ultra-low voltage logic circuits.
SOLUTION: An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and second power supply or ground. The gate and source of the first transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected to form an output connected to the bodies of the other transistors within the integrated circuit device.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于偏压超低电压逻辑电路的装置。 解决方案：集成电路器件包括多个晶体管和全局体偏置电路。 全局体偏置电路包括串联连接在电源和第二电源或地之间的第一晶体管和第二晶体管。 第一晶体管的栅极和源极连接到第二电源。 第一和第二晶体管的漏极和主体被连接以形成连接到集成电路器件内的其它晶体管的主体的输出端。

公开(公告)号：WO03001604A2

公开(公告)日：2003-01-03

申请号：PCT/EP0206202

申请日：2002-06-06

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and -0.5V for pFETs.

Abstract translation: 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。