公开(公告)号：DE3485686D1

公开(公告)日：1992-06-04

申请号：DE3485686

申请日：1984-12-18

Applicant: IBM

Inventor： CHEEK ELBERT ALSTON ,  THOMAS DAVID ROSS ,  ZBROZEK JOHN DENNIS

IPC: G11C29/04 ,  G06F9/06 ,  G06F9/445 ,  G06F12/06 ,  G11C17/00 ,  G06F11/20

Abstract: Data from a patch memory (23) is substituted for data in a read only memory (9) by applying high order addresses to a standard programmable logic array (19) having word lines (50a-50p, Figure 3). The address signals are separately applied to EXCLUSIVE OR circuits (27a-27g). The programmable logic array (19) is personalized to activate a line (21) at addresses to be substituted, and to provide logical zeros to the EXCLUSIVE OR circuits (27a-27g) which change during the patch. Only one word line is required for each continuous patch, which will vary in size on a patch-by-patch basis.