公开(公告)号：EP2641271A4

公开(公告)日：2014-03-19

申请号：EP11846296

申请日：2011-09-15

Applicant: IBM

Inventor： WANG XINLIN ,  CHEN XIANGDONG ,  CAI JIN

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L29/1041

公开(公告)号：EP1842239A4

公开(公告)日：2009-07-01

申请号：EP06718789

申请日：2006-01-19

Applicant: IBM

Inventor： CHEN XIANGDONG ,  YANG HAINING S

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

公开(公告)号：WO2006078740A2

公开(公告)日：2006-07-27

申请号：PCT/US2006001768

申请日：2006-01-19

Applicant: IBM ,  CHEN XIANGDONG ,  YANG HAINING S

Inventor： CHEN XIANGDONG ,  YANG HAINING S

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

Abstract translation: 公开了包括PMOSFET和NMOSFETS的应变MOSFET的半导体结构以及制造应变MOSFET的方法，其优化MOSFET中的应变，并且更特别地使MOSFET的一种（P或N）中的应变最大化并且使 在另一种（N或P）MOSFET的应变中，在PMOSFET和NMOSFET两者上形成具有原始全厚度的A应变诱导氮化镓氮化物涂层，其中应变诱导涂层在一种半导体器件中产生优化的全应变， 降低了另一种半导体器件的性能。 诱导氮化钛涂层的应变被蚀刻到比另一种半导体器件更薄的厚度，其中应变诱导涂层的减小的厚度在其它MOSFET中松弛并产生较小的应变。

公开(公告)号：WO2011056391A3

公开(公告)日：2011-08-04

申请号：PCT/US2010052989

申请日：2010-10-18

Applicant: IBM ,  PARK JAE-EUN ,  WANG XINLIN ,  CHEN XIANGDONG

Inventor： PARK JAE-EUN ,  WANG XINLIN ,  CHEN XIANGDONG

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7394 ,  H01L29/66325

Abstract: A method of forming a semiconductor device 100 having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure 15 on a first portion of the substrate 5 having a well 35 of a first conductivity. A source region 20 of a second conductivity and drain region 25 of the second conductivity is formed within the well 35 of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region 30 of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

Abstract translation: 一种形成具有不对称源极和漏极的半导体器件100的方法。 在一个实施例中，该方法包括在具有第一导电性的阱35的基板5的第一部分上形成栅极结构15。 在基板的与存在栅极结构的第一部分相邻的部分中，在第一导电体的阱35内形成具有第二导电性的第二导电和漏极区域25的源极区域20。 在漏区内形成具有第二导电性的掺杂区域30，以在半导体器件的漏极侧提供集成的双极晶体管，其中集电极由第一导电性阱提供，基极由漏极 第二电导率的区域和发射极由存在于漏极区域中的第二导电性的掺杂区域提供。 还提供了通过上述方法形成的半导体器件。

公开(公告)号：JP2005217391A

公开(公告)日：2005-08-11

申请号：JP2004312192

申请日：2004-10-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OUYANG QIQING C ,  CHEN XIANGDONG

IPC: H01L27/08 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/7841

Abstract: PROBLEM TO BE SOLVED: To provide the structure and manufacturing method of a high-performance electric field effect device.
SOLUTION: This MOS structure is equipped with a sort of conductive crystal Si main part, SiGe layer for which epitaxial growth has been performed on the Si main part that works as a buried channel of a hole, Si layer for which epitaxial growth has been performed on the SiGe layer that works as an electronic surface channel, and source/drain which accomodates strained SiGe for which conductive epitaxial growth has been performed in a way different from the Si main part. This SiGe source/drain forms hetero-junction and metallic bonding with the Si main part by overlapping each other with a tolerance of less than about 10 nm, preferably 5 nm. This heterostructure source/drain is useful for reducing a short channel effect. The foregoing structure increases hole mobility in a compressively strained SiGe channel, and therefore it is advantageous to PMOS. In typical embodiments, CMOS structure is provided on bulk and SOI.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供高性能电场效应器件的结构和制造方法。 解决方案：该MOS结构配备有一种导电晶体Si主要部分，对作为空穴的掩埋沟道的Si主要部分进行外延生长的SiGe层，外延生长的Si层 已经在用作电子表面通道的SiGe层上进行了，以及源/漏，其适应已经以不同于Si主要部分的方式进行导电外延生长的应变SiGe。 该SiGe源极/漏极通过以小于约10nm，优选5nm的公差彼此重叠而与Si主要部分形成异质结和金属结合。 该异质结构源极/漏极可用于减少短沟道效应。 上述结构增加了压缩应变SiGe沟道中的空穴迁移率，因此对PMOS是有利的。 在典型的实施例中，在本体和SOI上提供了CMOS结构。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005175478A

公开(公告)日：2005-06-30

申请号：JP2004353482

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN XIANGDONG ,  CHIDAMBARRAO DURESETI ,  WANG GENG

IPC: H01L27/08 ,  H01L21/8238 ,  H01L27/085 ,  H01L27/092 ,  H01L27/12 ,  H01L29/745 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/783

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET which dynamically varies the threshold voltage on an SOI.
SOLUTION: When a body control contact is provided adjacent to a transistor and between the transistor and a contact to a substrate or a well in which the transistor is formed, the substrate of the transistor can be connected to and disconnected from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold, resulting in good performance maintained even at low supply voltages and reduced power consumption/dissipation, which are particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate is disconnected from a voltage source in the "on" state) are avoided because the substrate is discharged when the transistor is switched to the "off" state. The transistor configuration can be used with n-type and p-type transistors in the case of complementary pairs or the like.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在SOI上动态地改变阈值电压的MOSFET。 解决方案：当身体控制触点设置在晶体管附近以及晶体管与形成晶体管的衬底或阱的触点之间时，晶体管的衬底可以连接到零点 （接地）或基本上任意的低电压，根据施加到晶体管的栅极的控制信号，以使晶体管呈现可变阈值，导致即使在低电源电压下也保持良好的性能，并且降低功耗/耗散，这特别是 有利于便携式电子设备。 避免浮体效应（当晶体管基板从“导通”状态的电压源断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。 在互补对等的情况下，晶体管配置可以与n型和p型晶体管一起使用。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：SG124357A1

公开(公告)日：2006-08-30

申请号：SG200600159

申请日：2006-01-09

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： YANG HAINING S ,  CHEN XIANGDONG ,  LEE YONG MENG ,  LIN WENHE

Abstract: A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer (40) over a transistor device (10A, 10B), ion implanting (44) a species (48) into the silicon nitride layer (40) to drive hydrogen from the silicon nitride layer (40), and annealing (60) to diffuse the hydrogen into a channel region of the transistor device (10A, 10B). The species (48) may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (0), carbon (C), boron (B),indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation (44) modulates atoms in the silicon nitride layer (40) such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region (30).

公开(公告)号：SG135103A1

公开(公告)日：2007-09-28

申请号：SG2007007990

申请日：2007-02-07

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHEN XIANGDONG ,  BAIOCCO CHRISTOPHER V ,  AJMERA ATUL ,  TEH YOUNG WAY ,  GAO WENZHI

Abstract: Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer (50) composed of a first oxide (130) and first nitride (40) layer is applied to a gate electrode (10) on a substrate (20), and a second spacer (60) composed of a second oxide (70) and a second nitride (80) layer is applied. Deep implanting of source and drain in the substrate (20) occurs, and removal of the second nitride (80), second oxide (70), and first nitride layers (40).

公开(公告)号：GB2487158A

公开(公告)日：2012-07-11

申请号：GB201206425

申请日：2010-10-18

Applicant: IBM

Inventor： PARK JAE-EUN ,  WANG XINLIN ,  CHEN XIANGDONG

IPC: H01L21/8249 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

Abstract: A method of forming a semiconductor device 100 having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure 15 on a first portion of the substrate 5 having a well 35 of a first conductivity. A source region 20 of a second conductivity and drain region 25 of the second conductivity is formed within the well 35 of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region 30 of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

公开(公告)号：SG158179A1

公开(公告)日：2010-01-29

申请号：SG2009086273

申请日：2006-01-09

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： YANG HAINING S ,  CHEN XIANGDONG ,  LEE YONG MENG ,  LIN WENHE

Abstract: A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer (40) over a transistor device (10A, 10B), ion implanting (44) a species (48) into the silicon nitride layer (40) to drive hydrogen from the silicon nitride layer (40), and annealing (60) to diffuse the hydrogen into a channel region of the transistor device (10A, 10B). The species (48) may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (0), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation (44) modulates atoms in the silicon nitride layer (40) such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region (30).