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    METHOD TO ENHANCE CMOS TRANSISTOR PERFORMANCE BY INDUCING STRAIN IN THE GATE AND CHANNEL
    1.
    发明公开
    METHOD TO ENHANCE CMOS TRANSISTOR PERFORMANCE BY INDUCING STRAIN IN THE GATE AND CHANNEL 审中-公开
    一种改善CMOS管效率THROUGH紧张的门和通道简介

    公开(公告)号：EP1815506A4

    公开(公告)日：2009-06-10

    申请号：EP05820872

    申请日：2005-11-10

    Applicant: IBM

    Inventor： YANG HAINING S

    IPC: H01L21/8238 ,  H01L21/336

    CPC classification number: H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

    Abstract: A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors (first and second type transistors) on a substrate (12). The method forms an optional oxide layer (52) on the NMOS transistors and the PMOS transistors and then covers the NMOS transistors and the PMOS transistors with a hard material (50) such as a silicon nitride layer. Following this, the method patterns portions of the hard material layer (50), such that the hard material layer remains only over the NMOS transistors. Next, the method heats (178, 204) the NMOS transistors and then removes the remaining portions of the hard material layer (50). By creating compressive stress in the gates (22) and tensile stress (70) in the channel regions of the NMOS transistors (NFETs), without creating stress in the gates (20) or channel regions of the PMOS transistors (PFETs), the method improves performance of the NFETs without degrading performance of the PFETs.

    STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETS
    3.
    发明公开
    STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETS 审中-公开
    结构与方法的字符串中CMOSFETS优化

    公开(公告)号：EP1842239A4

    公开(公告)日：2009-07-01

    申请号：EP06718789

    申请日：2006-01-19

    Applicant: IBM

    Inventor： CHEN XIANGDONG ,  YANG HAINING S

    IPC: H01L29/78 ,  H01L21/8238

    CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME
    6.
    发明公开
    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 有权
    VERBESSERTE CMOS-DIODEN MIT DOPPELGATE-LEITERN UND VERFAHREN ZU IHRER HERSTELLUNG

    公开(公告)号：EP2020029A4

    公开(公告)日：2009-09-09

    申请号：EP07761243

    申请日：2007-04-25

    Applicant: IBM

    Inventor： ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

    IPC: H01L23/62 ,  H01L21/329 ,  H01L29/739 ,  H01L29/78

    CPC classification number: H01L29/7391 ,  H01L29/66356

    Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

    Abstract translation: 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体而言，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电的第一栅极导体和p型导电的第二栅极导体分别位于衬底之上并且与第一和第二区域相邻。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 在第三区域与第二区域或第一区域之间的这种二极管结构中可以形成具有基础耗尽区的积聚区域，并且这种积聚区域的宽度优选地与第二或第一栅极 导体。

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