公开(公告)号：KR860000541B1

公开(公告)日：1986-05-08

申请号：KR820003647

申请日：1982-08-12

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  CUMMER DAVIC A

IPC: G06F12/02 ,  G11C11/406

Abstract: This circuit uses DMA conroller, for refreshing the DRAM and eliminating needs for special refresh conroller logic. The circuit comprising a divider counter and a latch circuit is coupled between the CPU and the highest priority channel of direct memory access controller. The highest priority DMA controller channel is used to refresh memory within the predetermined time intervals. The latch circuit is periodically set by the refresh clock signal and reset by an acknowledge signal from the direct memory access controller, at the completion of each refresh cycle.