公开(公告)号：KR860000541B1

公开(公告)日：1986-05-08

申请号：KR820003647

申请日：1982-08-12

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  CUMMER DAVIC A

IPC: G06F12/02 ,  G11C11/406

Abstract: This circuit uses DMA conroller, for refreshing the DRAM and eliminating needs for special refresh conroller logic. The circuit comprising a divider counter and a latch circuit is coupled between the CPU and the highest priority channel of direct memory access controller. The highest priority DMA controller channel is used to refresh memory within the predetermined time intervals. The latch circuit is periodically set by the refresh clock signal and reset by an acknowledge signal from the direct memory access controller, at the completion of each refresh cycle.

公开(公告)号：EP0085048A4

公开(公告)日：1986-01-07

申请号：EP81902344

申请日：1981-08-12

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G06F12/06 ,  G06F9/06

CPC classification number: G06F12/0623

Abstract: The extension of the size of memory, through the use of page signals in addressing such memory in previous inventions, made no provision for the possibility that a plurality of direct storage access channels which can operate simultaneously would be directed to the same extended addressing region of such storage. In order to provide for such access by the channels, this invention is directed to a computing system storage addressing apparatus (20, 40) which extends the addressing capability of an address bus (12) to enable direct storage (memory) storage access (DMA) channels (32, 33, 34 and 35), to operate simultaneously in the same or different storage pages. The computing system includes a processor (10), a plurality of storage devices (16), a data bus (14) and an address bus (12) interconnecting the processor and the storage devices, a DMA device (20) controls connection of the plurality of DMA channels to the address bus and data bus, a plurality of address registers (40) store page address signals loaded from the processor, and the address bus page address signals from an address register corresponding to a currently active DMA channel are gated to the address bus.

公开(公告)号：MX153198A

公开(公告)日：1986-08-21

申请号：MX19396382

申请日：1982-08-10

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G06F12/02 ,  G11C11/406 ,  G06F12/10

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：DE3176950D1

公开(公告)日：1989-01-12

申请号：DE3176950

申请日：1981-08-12

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G06F12/06

Abstract: A processor is provided with an address bus for manifesting a first set of address signals and a direct memory access control coupled to the address bus for manifesting a second lesser set of address signals. The processor accesses the storage by selectively operable channels. Programmable register are coupled to the address bus for manifesting a third set of address signals equal to, or less in number than the difference between the first and second setc. A decoder is responsive to the operation of the direct memory access control on behalf of a respective one of the operating channels for gating, to the address bus, the address signals manifested by the programmable register corresponding to the respective operating channel. This extends the addressing capability to enable direct storage access channels to operate simultaneously in the same or different storage page.

公开(公告)号：DE3265998D1

公开(公告)日：1985-10-10

申请号：DE3265998

申请日：1982-05-12

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN ,  SAENZ JESUS

IPC: G06F3/153 ,  G09G5/12 ,  G09G5/18 ,  G09G1/16

Abstract: Two controller units (11, 12) controlling a single input/ output device such as a cathode ray tube (CRT) are synchronized by a command signal. Upon appearance of the command signal, the slave controller unit (12), which may have been running unsynchronized with the master controller (11), is stopped at the time for vertical retrace and remains stopped until vertical retrace time for the master controller. At this point, the slave controller is restarted in synchronism with the master controller and remains synchronized so long as both master and slave receive the same clock and the same screen refresh parameters.

公开(公告)号：MY103253A

公开(公告)日：1993-05-29

申请号：MYPI19880315

申请日：1988-03-26

Applicant: IBM

Inventor： SAENZ JESUS ANDRES ,  EGGEBRECHT LEWIS CLARK

IPC: G06F1/24 ,  G06F3/023 ,  G06F3/00 ,  G06F3/02 ,  G06F13/00 ,  H04L25/38

Abstract: A SERIAL KEYBOARD INTERFACE (28) CONNECTS A SELF-SCANNING PROGRAMMABLE SERIALIZED KEYBOARD (40) TO THE SYSTEM BUS (10) OF A DATA PROCESSING SYSTEM. A CABLE (42) CONTAINING ONLY A CLOCK WIRE (52) AND A DATA WIRE (58) PROVIDES THE CONNECTION. THE KEYBOARD TRANSMITS A 9-BIT SCAN OUT CODE CONSISTING OF A START BIT FOLLOWED BY EIGHT SERIAL DATA BITS. THE KEYBOARD CLOCK LINE (52) IS CONNECTED TO THE CLOCK OR SHIFT TERMINAL OF A SERIAL-TO-PARALLEL SHIFT REGISTER ENCODER (62) FOR SHIFTING THE DATA BITS ON DATA LINE (58) INTO THE ENCODER WHICH HAS EIGHT PARALLEL OUTPUT DATA LINES (A,B,....G,H) CONNECTED TO THE SYSTEM BUS. WHEN THE ENCODER (62) CONTAINS A COMPLETE SCAN OUT FRAME, THE START BIT IS IN THE MOST SIGNIFICANT STAGE (H'') AND SETS THE D-TYPE LATCH (68) TO APPLY A CPU INTERRUPT REQUEST TO THE SYSTEM BUS (10). AT THIS TIME, THE O OUTPUT OF LATCH (68) PULLS DOWN THE DATA LINE TO GROUND POTENTIAL, THEREBY DISABLING THE DATA LINE AND PREVENTING FURTHER KEYBOARD TRANSMISSION OF DATA. WHEN THE INTERUUPT REQUEST IS GRANTED BY THE CPU, A CLEAR SIGNAL RESETS LATCH (68) TO REMOVE GROUND POTENTIAL FROM DATA LINE (58) AND THEREBY PERMIT FURTHER TRANSMISSION OF DATA.(FIG 2)

公开(公告)号：HK18590A

公开(公告)日：1990-03-16

申请号：HK18590

申请日：1990-03-08

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  KUMMER DAVID ALLEN

IPC: G06F12/06

Abstract: PCT No. PCT/US81/01078 Sec. 371 Date Mar. 31, 1983 Sec. 102(e) Date Mar. 31, 1983 PCT Filed Aug. 12, 1981 PCT Pub. No. WO83/00576 PCT Pub. Date Feb. 17, 1983.A computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) storage access (DMA) channels to operate simultaneously in the same or different storage page. The computing system includes a processor, a plurality of storage devices, a data bus and an address bus interconnecting the processor and the storage devices, a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from an address register means corresponding to a currently active DMA channel.

公开(公告)号：DE3267005D1

公开(公告)日：1985-11-28

申请号：DE3267005

申请日：1982-06-29

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  SAENZ JESUS ANDRES

IPC: G06F1/24 ,  G06F3/00 ,  G06F3/02 ,  G06F13/00 ,  H04L25/38 ,  G06F3/023

Abstract: A serial keyboard interface (28) connects a self scanning programmable serialized keyboard (40) to the system bus (10) of a data processing system. A cable (42) containing only a clock wire (52) and a data wire (58) provides the connection. The keyboard transmits a 9-bit scan out code consisting of a start bit followed by eight serial data bits. The keyboard clock line (52) is connected to the clock or shift terminal of a serial-to-parallel shift register encoder (62) for shifting the data bits on data line (58) into the encoder which has eight parallel output data lines (A, B . . . G, H) connected to the system bus. When the encoder (62) contains a complete scan out frame, the start bit is in the most significant stage (h') and sets the D-type latch (68) to apply a CPU interrupt request to the system bus (10). At this time, the &upbar& Q output of latch (68) pulls down the data line to ground potential, thereby disabling the data line and preventing further keyboard transmission of data. When the interrupt request is granted by the CPU, a clear signal resets latch (68) to remove ground potential from data line (58) and thereby permit further transmission of data.

公开(公告)号：HK81490A

公开(公告)日：1990-10-19

申请号：HK81490

申请日：1990-10-11

Applicant: IBM

Inventor： BRADLEY DAVID JOHN ,  GIBBS DENNIS DARRELL ,  KOSTUCH DONALD JAMES ,  MARTIN JAMES STUART ,  EGGEBRECHT LEWIS CLARK

IPC: G06F12/06

公开(公告)号：HK32189A

公开(公告)日：1989-04-28

申请号：HK32189

申请日：1989-04-20

Applicant: IBM

Inventor： EGGEBRECHT LEWIS CLARK ,  SAENZ JESUS ANDRES

IPC: G06F1/24 ,  G06F3/00 ,  G06F3/02 ,  G06F13/00 ,  H04L25/38 ,  G06F3/023

Abstract: A serial keyboard interface (28) connects a self scanning programmable serialized keyboard (40) to the system bus (10) of a data processing system. A cable (42) containing only a clock wire (52) and a data wire (58) provides the connection. The keyboard transmits a 9-bit scan out code consisting of a start bit followed by eight serial data bits. The keyboard clock line (52) is connected to the clock or shift terminal of a serial-to-parallel shift register encoder (62) for shifting the data bits on data line (58) into the encoder which has eight parallel output data lines (A, B . . . G, H) connected to the system bus. When the encoder (62) contains a complete scan out frame, the start bit is in the most significant stage (h') and sets the D-type latch (68) to apply a CPU interrupt request to the system bus (10). At this time, the &upbar& Q output of latch (68) pulls down the data line to ground potential, thereby disabling the data line and preventing further keyboard transmission of data. When the interrupt request is granted by the CPU, a clear signal resets latch (68) to remove ground potential from data line (58) and thereby permit further transmission of data.