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公开(公告)号:JPH1041478A
公开(公告)日:1998-02-13
申请号:JP8620597
申请日:1997-04-04
Applicant: IBM
IPC: H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
Abstract: PROBLEM TO BE SOLVED: To provide an electrode structure which can be formed without mechanically, chemically polishing or patterning a thick electrode layer by a method wherein a memory device possessed of ferroelectric material or capacitor dielectric material is sandwiched between a plate electrode and a stacked electrode. SOLUTION: An electric device is formed by the use of a composite electrode. A device 40 is equipped with an insulating or semiconductor substrate 12, a contact region 14 formed inside the substrate 12, and a dielectric layer 1 formed on the substrate 12. A conductive structure 40 is wholly or partially brought into electric contact with the top of a conductor plug 2. A capacitor dielectric material layer 9 nearly uniform in thickness is formed on the exposed part of a stacked electrode. A plate electrode 20 is electrically insulated from the stacked electrode but electrically connected to the plate electrode of another device formed on the same substrate 12. By this setup, a memory device such as a capacitive memory device used for a DRAM can be formed.
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公开(公告)号:JPH1041474A
公开(公告)日:1998-02-13
申请号:JP8622397
申请日:1997-04-04
Applicant: IBM
Inventor: LAUR EDMUND ACOSTA , JAMES HARTFIEL COMFORT , ALFRED GRILL , DAVID EDWARD KOTTEKI , CATHERINE LYNN SANGER
IPC: H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
Abstract: PROBLEM TO BE SOLVED: To enable a dielectric structure to be formed inside a non-planar capacitor and a ferroelectric memory cell by a method wherein a recess where a dielectric is deposited is demarcated by a gap between a plate electrode and a stacked electrode. SOLUTION: A capacitor structure 100 is composed of a first electrode or a plate electrode 1 and a second electrode or a stacked electrode 2 surrounded with the plate electrode 1. The plate electrode 1 is isolated from the stacked electrode 2 by a narrow gap filled with a capacitor dielectric body 3. A conductive plug 4 buried in a dielectric body 5 is brought into contact with a conductive region 6 on a board 20. A gap can be formed between the plate electrode 1 and the stacked electrode 2 in a final structure or between one or more sacrifice materials and either the plate electrode 1 or the stacked electrode 2. By this setup, the dielectric body 3 is not required to be deposited through a conformal process such as a chemical vapor deposition method.
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