公开(公告)号：JP2011113119A

公开(公告)日：2011-06-09

申请号：JP2009266286

申请日：2009-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MATSUO HISATO ,  TANAKA KEISUKE ,  DEMURA MASAYUKI

IPC: G06F12/00 ,  G06F13/362

CPC classification number: G06F13/161 ,  G06F13/1673 ,  Y02D10/14

Abstract: PROBLEM TO BE SOLVED: To provide a memory access device for sharing a buffer for data flows of an information device and a main memory for a processor. SOLUTION: An arbiter unit assigns access requests to the memory from a plurality of functional blocks sequentially by a round-robin method with a predetermined transfer length. (a) Data transfer from a functional block is split into partial transfers by a predetermined transfer length, and a plurality of partial transfers are performed according to a band for data transfer in one round-robin cycle. (b) The plurality of partial transfers have different priorities, and the priorities are programmably set up so that the required band of data transfer from all functional blocks may be satisfied by alternate transfer of the partial transfers from different functional blocks. (c) An access from the processor is executed so that the number of accesses from the processor to the memory may exert less effect on bands for data flow transfers with top priority and with a predetermined transfer length (CPU transfer length) in predetermined intervals between the transfer blocks. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于共享用于处理器的信息设备和主存储器的数据流的缓冲器的存储器访问设备。 解决方案：仲裁器单元通过具有预定传送长度的循环方法顺序地从多个功能块向存储器分配访问请求。 （a）从功能块的数据传送被分割成预定传送长度的部分传送，并且根据用于一轮循环的数据传送的频带执行多个部分传送。 （b）多个部分传送具有不同的优先级，并且可编程地设置优先级，使得可以通过从不同功能块的部分传输的交替传送来满足来自所有功能块的所需数据传送频带。 （c）执行来自处理器的访问，使得从处理器到存储器的访问次数可以对具有最高优先级的数据流传输的频带施加较小的影响，并且以预定的传送长度（CPU传送长度）以 传输块。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2000224049A

公开(公告)日：2000-08-11

申请号：JP1346899

申请日：1999-01-21

Applicant: IBM

Inventor： NAKAMURA AKIO ,  TAMURA TETSUYA ,  DEMURA MASAYUKI

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To detect error correction in a short time and to execute error correction by adding an error correction code to one or more error detection code blocks to which the error detection code is attached, calculating an error value by using the error correction code respectively included in data series, correcting the syndrome value of the error detection code according to the value and detecting error occurrence. SOLUTION: A selector 126 operates in accordance with the control of a chain searching part 112 of an error correction block 10 and selects a root inputted from a position counter 110, when it is shown that there is no error in detected data. Then, it outputs it to error detection code EDC correction difference calculating parts 14a and 14b and a syndrome correction difference calculating part 18. A selector 128 operates in accordance with the control of the part 112 of the block 10, selects a numerical value 0 when it is shown that an error does not exist in detected data, selects size data when an error exists in the detected data and outputs to the parts 14a and 14b.

公开(公告)号：JPH11274941A

公开(公告)日：1999-10-08

申请号：JP2487598

申请日：1998-02-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： NAGURA HIROHISA ,  DEMURA MASAYUKI ,  TANAKA KEISUKE ,  TAMURA TETSUYA

IPC: G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/29

CPC classification number: G06F11/1008 ,  G11B20/10 ,  G11B20/18 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/2909 ,  H03M13/293

Abstract: PROBLEM TO BE SOLVED: To shorten the total processing time needed for correction of errors by taking out two position data adjacent to each other in a single line that is sorted as an erased line and also two information data related to the position data and then repetitively correcting two position data based on the patterns included in those position and information data until all lines are corrected. SOLUTION: The coding data on a row 1 included in every group which are stored in the memory sections 14 and 15 and taken out of a main memory 12 are sent to a wrong data position/pattern generator 16 via a line 24. Thus, the information blocks are generated. The generator 16 detects via an erased line pointer of a register 32 whether the wrong data under processing belong to an erased line or non-erased line. Then generator 16 calculates the wrong data position of the erased line to generate an information block, including a bit pattern that corrects the wrong data position and sends the information block to a memory section 14A of a buffer memory 13 to assemble the rows. It is checked whether all rows have been processed, and these operations are repeated until all the rows are have been corrected.

Abstract translation: 要解决的问题：通过在排列为擦除行的单行中取出彼此相邻的两个位置数据以及与位置数据相关的两个信息数据，然后重复地缩短校正错误所需的总处理时间 基于包括在那些位置和信息数据中的模式来校正两个位置数据，直到所有行被校正。 解决方案：存储在存储器部分14和15中并从主存储器12中取出的每个组中包括的行1上的编码数据经由线路24被发送到错误的数据位置/模式发生器16.因此， 生成信息块。 发生器16经由寄存器32的擦除行指针检测处理中的错误数据是否属于擦除行或未擦除行。 然后，发生器16计算擦除行的错误数据位置，以产生信息块，包括校正错误数据位置的位模式，并将信息块发送到缓冲存储器13的存储器部分14A以组合行。 检查是否已经处理了所有行，并重复这些操作，直到所有行已被更正。

公开(公告)号：JP2000020333A

公开(公告)日：2000-01-21

申请号：JP18482798

申请日：1998-06-30

Applicant: IBM

Inventor： NAKAMURA AKIO ,  TAMURA TETSUYA ,  DEMURA MASAYUKI ,  NAGURA HIROHISA

IPC: G06F11/10 ,  H03M13/01 ,  H03M13/15

Abstract: PROBLEM TO BE SOLVED: To make it possible to decode a linear cyclic code in a small hardware quantity by repeating a specific recurrence formula by a polynomial calculation means until the degree of the polynomial becomes less than a specific value to calculate an error position polynomial and an error value polynomial and calculating a disappearance position polynomial from disappearance position data. SOLUTION: A polynomial calculating operation part 14 calculates an error position polynomial σ(x) and an error value polynomial ω(x) by repeating respective recurrence formulae σi=σi-2(x)+Qi(x).σi-1(x) and ωi=ωi-2(x)+Qi(x).ωi-1(x) (provided that Qi(x) is a quatient of ωi-2(x)/ωi-1(x), σi-1(x)=1, ωi-1(x)=x2t, σ0(x)=1, ω0(x)=M(x) and M(x) is a corrected syndrom polynomial) until the degree of the polynomial ωi becomes less than [(d+h-1)/2] (provided that [] is the Gauss' symbol, (d) is the minimum Hamming distance and (h) is the number of disappearance positions. Then, a disappearance position polynomial λ(x) is calculated from disappearance position data αi.

公开(公告)号：JPH11185399A

公开(公告)日：1999-07-09

申请号：JP34643897

申请日：1997-12-16

Applicant: IBM

Inventor： DEMURA MASAYUKI ,  TAMURA TETSUYA ,  SASAKI AKIRA ,  ITAGAKI HIROSHI

IPC: G11B20/12 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

Abstract: PROBLEM TO BE SOLVED: To provide a method performing the coding of an ECC(error-correcting code) block efficiently in order to enhance a write performance to a storage device in which an ECC block having liner codes like a Reed-Solomon code is adopted. SOLUTION: At the time of calculating an ECC block F2 having a PO part q2 posterior to an updating by updating the data f1 of the data sector of one parts being in plural data sectors constituting an ECC block F1 having the PO part q1 generated with linear codes like the Reed-Solomon code with data f2 , and exclusive OR f1 +f2 between data f1 to be updated and updated f2 is calculated by operating ECC blocks F1 +F2 being an exclusive OR between source data parts the ECC block F1 prior to the updating and the ECC block F2 posterior to the updating. Exclusive ORs among data sectors which are not updated become zero. Next, when codings are performed as to the ECC blocks F1 +F2 being the exclusive OR, an OP part having the form of an exclusive OR q1 +q2 is obtained by the linear property of the Reed-Solomon code. Then, q2 can be calculated by the exclusive OR between q1 +q2 and q1 .

公开(公告)号：JPH10283119A

公开(公告)日：1998-10-23

申请号：JP8984497

申请日：1997-04-09

Applicant: IBM JAPAN

Inventor： TAMURA TETSUYA ,  DEMURA MASAYUKI ,  ITAGAKI HIROSHI ,  YAMADA MITSUHARU

IPC: G06F3/06 ,  G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03M13/00 ,  H04L13/08

Abstract: PROBLEM TO BE SOLVED: To perform efficient data transfer for performing correction in real time by dynamically changing a transfer mode corresponding to the state of a decoder and adding one buffer constituted of plural banks further. SOLUTION: The transfer mode is dynamically changed corresponding to the state of the decoder and one buffer constituted of the two or more banks is newly added further. For instance, in a DVD reproduction system, signals read by a pickup are inputted to a DVD control block and sent to a decoding block 20. Data received in the decoding block 20 are error-corrected by the buffer, an MPU 20B and the decoder 20C provided inside the decoding block 20 connected by a common bus, decoded in real time and transmitted to a host side. In this case, in the decoding block 20, the buffer is constituted of a first buffer 20A-1 and a second buffer 20A-2. Then, the second buffer 20A-2 is provided with the two banks 26 and 28.