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公开(公告)号：DE69424229T2
公开(公告)日：2000-11-30
申请号：DE69424229
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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2.发明专利
公开(公告)号：CA2122170A1
公开(公告)日：1995-01-09
申请号：CA2122170
申请日：1994-04-26
Applicant: IBM
Inventor： HASSNER MARTIN A , KARNIN EHUD D , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: COMBINATION PARALLEL/SERIAL EXECUTION OF SEQUENTIAL ALGORITHM FOR DATA COMPRESSION/DECOMPRESSION An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer compresses an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：AT205012T
公开(公告)日：2001-09-15
申请号：AT96304352
申请日：1996-06-10
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , TAMURA TETSUYA , WINOGRAD SHMUEL
Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
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公开(公告)号：DE69614772T2
公开(公告)日：2002-07-04
申请号：DE69614772
申请日：1996-06-10
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , TAMURA TETSUYA , WINOGRAD SHMUEL
Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
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公开(公告)号：SG45138A1
公开(公告)日：1998-01-16
申请号：SG1996000352
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELLIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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Patent Agency Ranking
公开(公告)号：JP2000020333A
公开(公告)日：2000-01-21
申请号：JP18482798
申请日：1998-06-30
Applicant: IBM
Inventor： NAKAMURA AKIO , TAMURA TETSUYA , DEMURA MASAYUKI , NAGURA HIROHISA
Abstract: PROBLEM TO BE SOLVED: To make it possible to decode a linear cyclic code in a small hardware quantity by repeating a specific recurrence formula by a polynomial calculation means until the degree of the polynomial becomes less than a specific value to calculate an error position polynomial and an error value polynomial and calculating a disappearance position polynomial from disappearance position data. SOLUTION: A polynomial calculating operation part 14 calculates an error position polynomial σ(x) and an error value polynomial ω(x) by repeating respective recurrence formulae σi=σi-2(x)+Qi(x).σi-1(x) and ωi=ωi-2(x)+Qi(x).ωi-1(x) (provided that Qi(x) is a quatient of ωi-2(x)/ωi-1(x), σi-1(x)=1, ωi-1(x)=x2t, σ0(x)=1, ω0(x)=M(x) and M(x) is a corrected syndrom polynomial) until the degree of the polynomial ωi becomes less than [(d+h-1)/2] (provided that [] is the Gauss' symbol, (d) is the minimum Hamming distance and (h) is the number of disappearance positions. Then, a disappearance position polynomial λ(x) is calculated from disappearance position data αi.
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公开(公告)号：JPH11185399A
公开(公告)日：1999-07-09
申请号：JP34643897
申请日：1997-12-16
Applicant: IBM
Inventor： DEMURA MASAYUKI , TAMURA TETSUYA , SASAKI AKIRA , ITAGAKI HIROSHI
Abstract: PROBLEM TO BE SOLVED: To provide a method performing the coding of an ECC(error-correcting code) block efficiently in order to enhance a write performance to a storage device in which an ECC block having liner codes like a Reed-Solomon code is adopted. SOLUTION: At the time of calculating an ECC block F2 having a PO part q2 posterior to an updating by updating the data f1 of the data sector of one parts being in plural data sectors constituting an ECC block F1 having the PO part q1 generated with linear codes like the Reed-Solomon code with data f2 , and exclusive OR f1 +f2 between data f1 to be updated and updated f2 is calculated by operating ECC blocks F1 +F2 being an exclusive OR between source data parts the ECC block F1 prior to the updating and the ECC block F2 posterior to the updating. Exclusive ORs among data sectors which are not updated become zero. Next, when codings are performed as to the ECC blocks F1 +F2 being the exclusive OR, an OP part having the form of an exclusive OR q1 +q2 is obtained by the linear property of the Reed-Solomon code. Then, q2 can be calculated by the exclusive OR between q1 +q2 and q1 .
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公开(公告)号：JPH10283119A
公开(公告)日：1998-10-23
申请号：JP8984497
申请日：1997-04-09
Applicant: IBM JAPAN
Inventor： TAMURA TETSUYA , DEMURA MASAYUKI , ITAGAKI HIROSHI , YAMADA MITSUHARU
Abstract: PROBLEM TO BE SOLVED: To perform efficient data transfer for performing correction in real time by dynamically changing a transfer mode corresponding to the state of a decoder and adding one buffer constituted of plural banks further. SOLUTION: The transfer mode is dynamically changed corresponding to the state of the decoder and one buffer constituted of the two or more banks is newly added further. For instance, in a DVD reproduction system, signals read by a pickup are inputted to a DVD control block and sent to a decoding block 20. Data received in the decoding block 20 are error-corrected by the buffer, an MPU 20B and the decoder 20C provided inside the decoding block 20 connected by a common bus, decoded in real time and transmitted to a host side. In this case, in the decoding block 20, the buffer is constituted of a first buffer 20A-1 and a second buffer 20A-2. Then, the second buffer 20A-2 is provided with the two banks 26 and 28.
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公开(公告)号：JPH097311A
公开(公告)日：1997-01-10
申请号：JP13337896
申请日：1996-05-28
Applicant: IBM
Inventor： MAACHIN AURERIAANO HASUNAA , TAMURA TETSUYA , SHIYUMUERU UINOGURAADO
Abstract: PROBLEM TO BE SOLVED: To achieve a parallel ML processing of an analog signal in an RLL encoding channel by integrating the analog signal weighted by a specified coefficient orthogonal over a symbol period. SOLUTION: An analog read back signal polluted by a noise from an optical recording medium 10 is converted to an equalization signal e(t) by an equalizer 12 and sent to a peak detection timing unit 13. The signal e(t) is weighted by a different specified Walsh's weight function of the signal e(t) by an analog Walsh conversion vector generator-sample unit 15. The unit 15 contains a vector generator 6, a sampling switch 17, a clock 18 which outputs a symbol clock pulse at each cycle of a PLL clock 14 to define a symbol clock period, a detector 19 to output an MLn bit decoding symbol to a line 20 corresponding to the signal e(t) and a tracking unit 21 to generate a phase correction signal Δϕ.
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公开(公告)号：JPH0795093A
公开(公告)日：1995-04-07
申请号：JP15234294
申请日：1994-07-04
Applicant: IBM
Inventor： MAATEIN AURERIAANO HASUNAA , EUDO DOFU KAANIN , UI SUIEGERUSOON , TAMURA TETSUYA
Abstract: PURPOSE: To provide data compression/expansion device and method for executing LZ1 algorithm by a module type architecture. CONSTITUTION: Sequential data compression algorithm especially useful in the case that data compression is requested in a device (discriminated from a host) controller 12 is executed. A history buffer 22 compresses the array of the (i) pieces of the same horizontal slice units, the respective slice units store the (j) pieces of symbols for defining the (j) pieces of different blocks and the symbols inside the respective slice units are accurately sectioned by the (i) pieces of the symbols. The symbols inside the string of the (i) pieces of input symbols are parallelly compared with the symbols previously stored inside the slice unit by the (i) pieces of comparators so as to identify the matching sequence of the symbols.
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