aparelho de interface elástica, método para o mesmo e respectivo sistema

    公开(公告)号:BRPI0009250B1

    公开(公告)日:2016-08-23

    申请号:BR0009250

    申请日:2000-03-03

    Applicant: IBM

    Abstract: patente de invenção: "aparelho de interface elástica e método para o mesmo". um aparelho e método de interface elástica são implementados. a interface elástica inclui uma pluralidade de unidades de armazenamento para armazenar um fluxo de valores de dados, onde cada unidade de armazenamento seqüencialmente armazena membros dos respectivos conjuntos de valores de dados. cada valor de dados é armazenado para um número predeterminado de períodos de um clock local. o circuitamento de seleção pode ser acoplado com as unidades de armazenamento para selecionar os respectivos valores de dados a partir do fluxo de dados para armazenamento na unidade de armazenamento correspondente. os dados são seqüencialmente emitidos a partir de cada unidade de armazenamento em sincronia com o clock local em um ciclo alvo do clock local.

    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR

    公开(公告)号:CA2365288C

    公开(公告)日:2009-05-05

    申请号:CA2365288

    申请日:2000-03-03

    Applicant: IBM

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialisation procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latchin g of the data signals is adjusted so that a latching transition is substantially centred in a data valid window.

    5.
    发明专利
    未知

    公开(公告)号:ES2195873T3

    公开(公告)日:2003-12-16

    申请号:ES00907775

    申请日:2000-03-03

    Applicant: IBM

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

    Dynamic wave-chained interface and methods therefor

    公开(公告)号:CZ20013179A3

    公开(公告)日:2002-02-13

    申请号:CZ20013179

    申请日:2000-03-03

    Applicant: IBM

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

    Dynamic wave-pipelined interface apparatus and methods therefor

    公开(公告)号:AU2925200A

    公开(公告)日:2000-09-28

    申请号:AU2925200

    申请日:2000-03-03

    Applicant: IBM

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

    8.
    发明专利
    未知

    公开(公告)号:AT239945T

    公开(公告)日:2003-05-15

    申请号:AT00907773

    申请日:2000-03-03

    Applicant: IBM

    Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR

    公开(公告)号:HU0105099A2

    公开(公告)日:2002-04-29

    申请号:HU0105099

    申请日:2000-03-03

    Applicant: IBM

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

    Elastic interface apparatus and method therefor

    公开(公告)号:AU2925000A

    公开(公告)日:2000-09-28

    申请号:AU2925000

    申请日:2000-03-03

    Applicant: IBM

    Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

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