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    METHOD AND DEVICE FOR GENERATING SYNCHRONIZED CLOCK SIGNAL
    1.
    发明专利
    METHOD AND DEVICE FOR GENERATING SYNCHRONIZED CLOCK SIGNAL 失效

    公开(公告)号：JPH11259167A

    公开(公告)日：1999-09-24

    申请号：JP4999

    申请日：1999-01-04

    Applicant: IBM

    Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT PAUL ,  MUHICH JOHN STEPHEN

    IPC: G06F1/04 ,  G06F1/10 ,  H03L7/00 ,  H03L7/07 ,  H04L7/02

    Abstract: PROBLEM TO BE SOLVED: To provide a clock generating device useful for a high-speed subminiature electronic device by making a 1st series of signals succeeding to one another in response to a 1st phase difference, a 2nd series of signals succeed to one another in response to a 2nd phase difference, and the 1st series of signals respond to the 2nd phase difference. SOLUTION: In response to a reference signal from a SAW generator 104, a 1st DLL digital locked loop rotating means 118 generates 1st signals and in response to a reference signal from a SAW transmitter 104, a 2nd DLL rotating means 116 generates 2nd signals respectively. A clock frequency divider 130 divides the frequency of a 1st clock signal by a multiple of 2 with the 1st series of signals and supplies the result to an off-chip memory 108. With the 2nd series of signals, a 2nd clock signal is supplied to a clock distribution system 128. Those series of signals are made to succeed to one another in response to the phase differences of phase detectors 132 and 134.

    CLOCK SIGNAL SUPPLY METHOD AND DEVICE
    2.
    发明专利
    CLOCK SIGNAL SUPPLY METHOD AND DEVICE 失效

    公开(公告)号：JPH11316616A

    公开(公告)日：1999-11-16

    申请号：JP5099

    申请日：1999-01-04

    Applicant: IBM

    Inventor： DREPS DANIEL MARK ,  MASLEID ROBERT PAUL ,  MUHICH JOHN STEPHEN

    IPC: G06F1/06 ,  G06F1/04 ,  G06F1/10 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099

    Abstract: PROBLEM TO BE SOLVED: To reduce the phase difference between clock signals and also to reduce the disturbance in clock signals caused by substitution by substituting a selected 1st clock signal for a 2nd signal among plural signals whose phases are shifted to the 1st clock signal for reduction of the phase difference between the 1st clock signal and a reference clock signal. SOLUTION: A 1st clock signal is selected out of four internal source signals of a rotation means 14 and outputted. A phase detector 20 compares a reference clock signal 21 with the 1st clock signal and generates an output signal to show the phase difference between the signal 21 and the 1st clock signal. Then the output signal is fed back to the means 14 through a digital filter 22. The means 14 delays the source to be selected for the 1st clock signal by changing continuously one of plural source signals that is kept in a halt state to another. Then the means 14 locks the phase of a feedback clock signal against the signal 21.

    Interface between self-repair chips
    4.
    发明专利
    Interface between self-repair chips 审中-公开
    自我修复界面

    公开(公告)号：JP2004220598A

    公开(公告)日：2004-08-05

    申请号：JP2003431365

    申请日：2003-12-25

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BECKER WIREN DALE ,  DREPS DANIEL MARK ,  FERRAIOLO FRANK D ,  HARIDASS ANAND ,  REESE ROBERT JAMES

    IPC: G06F13/00 ,  G06F11/26 ,  H01L21/66

    CPC classification number: H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for managing a set of signal paths of a chip and to provide a computer instruction. SOLUTION: A defective signal path among the set of signal paths of the chip is detected. A route of a signal is specified again via the set of signal paths in response to detection of the defective signal path, the defective signal path is eliminated from the set of signal paths and the signal is transmitted by using the remaining data signal path of the set of signal paths and using an excess signal path. In addition, the chip is a data source, a test pattern is generated by the data source, the test pattern is transmitted to a data destination by using the set of signal paths, the received pattern is compared with expected data at the data destination and whether or not the defective signal path exists is determined by utilizing this comparison result. COPYRIGHT: (C)2004,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于管理芯片的一组信号路径并提供计算机指令的方法和装置。 解决方案：检测芯片组的信号路径中的有缺陷的信号路径。 响应于缺陷信号路径的检测，再次通过信号路径集合指定信号的路线，从信号路径组中消除了缺陷信号路径，并且通过使用信号路径的剩余数据信号路径来发送信号 一组信号路径并使用多余的信号路径。 另外，芯片是数据源，由数据源产生测试模式，通过使用该组信号路径将测试模式发送到数据目的地，将接收的模式与数据目的地的预期数据进行比较， 通过利用该比较结果确定存在缺陷信号路径。 版权所有（C）2004，JPO＆NCIPI

    DYNAMIC LINE TERMINATING CLAMPING CIRCUIT
    5.
    发明专利
    DYNAMIC LINE TERMINATING CLAMPING CIRCUIT 失效

    公开(公告)号：JPH11330944A

    公开(公告)日：1999-11-30

    申请号：JP6927499

    申请日：1999-03-15

    Applicant: IBM

    Inventor： COTEUS PAUL W ,  DREPS DANIEL MARK ,  FRANK DAVID FERRAYORO

    IPC: H03K5/007 ,  H03K19/0175 ,  H04L25/02

    Abstract: PROBLEM TO BE SOLVED: To attain the fast bus pumping by placing a 2nd transistor TR between a 2nd reference voltage and an intermediate node and only the 1st and 2nd inverters connected to each other between the intermediate node and a 1st TR and between the intermediate node and the control input of the 2nd TR respectively. SOLUTION: The inverters 40 and 42 have the switching voltage threshold of about 0.7 VDD and about 0.3 VDD respectively. Therefore, a transistor TR 32 is turned off when the signal voltage level rises up to 0.7 VDD at a terminating node 30. In the same way, a TR 36 is turned on when the signal voltage level dropped down to 0.3 VDD at an intermediate node 30 and then turned off when the signal voltage rises higher than 0.3 VDD. The node 30 is clamped at VSS by the operations of both TR 32 and 36 when a driver 24 drives a signal line 22 at a high logical level.

    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR
    7.
    发明专利
    DYNAMIC WAVE-PIPELINED INTERFACE APPARATUS AND METHODS THEREFOR 未知

    公开(公告)号：CA2365288C

    公开(公告)日：2009-05-05

    申请号：CA2365288

    申请日：2000-03-03

    Applicant: IBM

    Inventor： FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES ,  DREPS DANIEL MARK

    IPC: G06F13/38 ,  G06F13/42 ,  H04L7/04

    Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialisation procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latchin g of the data signals is adjusted so that a latching transition is substantially centred in a data valid window.

    10.
    发明专利
    未知

    公开(公告)号：AT239945T

    公开(公告)日：2003-05-15

    申请号：AT00907773

    申请日：2000-03-03

    Applicant: IBM

    Inventor： DREPS DANIEL MARK ,  FERRAIOLO FRANK DAVID ,  GOWER KEVIN CHARLES

    IPC: G06F13/42 ,  G06F5/06 ,  H04L7/00 ,  H04L7/02

    Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

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