公开(公告)号：SG108241A1

公开(公告)日：2005-01-28

申请号：SG200101030

申请日：2001-02-22

Applicant: IBM

Inventor： DOUGLAS DUANE COOLBAUGH ,  GREGORY GOWER FREEMAN ,  SESHADRI SUBBANNA

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/737 ,  H01L27/08

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.