公开(公告)号：MY124964A

公开(公告)日：2006-07-31

申请号：MYPI20004901

申请日：2000-10-18

Applicant: IBM

Inventor： DOUGLAS D COOLBAUGH ,  DAVID L HARAME ,  JAMES S DUNN ,  PETER J GEISS ,  PETER B GRAY ,  KATHRYN T SCHONENBERG ,  STEPHEN A ST ONGE ,  SESHADRI SUBBANNA

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A METHOD FOR FORMING A BICMOS INTEGRATED CIRCUIT IS PROVIDED WHICH COMPRISES THE STEPS OF: (A) FORMING A FIRST PORTION OF A BIPOLAR DEVICE IN FIRST REGIONS OF A SUBSTRATE; (B) FORMING A FIRST PROTECTIVE LAYER OVER SAID FIRST REGIONS TO PROTECT SAID FIRST PORTION OF SAID BIPOLAR DEVICES: (C) FORMING FIELD EFFECT TRANSISTOR DEVICES IN SECOND REGIONS OF SAID SUBSTRATE; (D) FORMING A SECOND PROTECTIVE LAYER OVER SAID SECOND REGIONS OF SAID SUBSTRATE TO PROTECT SAID FIELD EFFECT TRANSISTOR DEVICES; (E) REMOVING SAID FIRST PROTECTIVE LAYER; (F) FORMING A SECOND PORTION OF SAID BIPOLAR DEVICES IN SAID FIRST REGIONS OF SAID SUBSTRATE; AND (G) REMOVING SAID SECOND PROTECTIVE LAYER.(FIG 1)

公开(公告)号：MY124875A

公开(公告)日：2006-07-31

申请号：MYPI20010539

申请日：2001-02-07

Applicant: IBM

Inventor： SESHADRI SUBBANNA ,  DOUGLAS DUANE COOLBAUGH ,  GREGORY G FREEMAN

IPC: H01L21/331 ,  H01L31/119 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/108 ,  H01L29/73 ,  H01L29/737 ,  H01L29/76 ,  H01L29/94

Abstract: A METHOD OF FORMING A POLY-POLY CAPACITOR (49), A MOS TRANSISTOR (18), AND A BIPOLAR TRANSISTOR (48) SIMULTANEOUSLY ON A SUBSTRATE (10) COMPRISING THE STEPS OF THE DEPOSITING AND PATTERNING A FIRST LAYER (26) OF POLYSILICON ON THE SUBSTRATE TO FORM A FIRST PLATE ELECTRODE CAPASITOR AND ON AN ELECTRODE OF THE MOS TRANSISTOR, AND DEPOSISTING AND PATTERINING A SECOND LAYER (42) OF POLYSILICON ON THE SUBTRATE TO FORM A SECOND PLATE ELECTRODE OF SAID CAPACITOR AND AN ELECTRODE OF THE BIPOLAR TRANSISTOR.(FIG. 1F)

公开(公告)号：SG108241A1

公开(公告)日：2005-01-28

申请号：SG200101030

申请日：2001-02-22

Applicant: IBM

Inventor： DOUGLAS DUANE COOLBAUGH ,  GREGORY GOWER FREEMAN ,  SESHADRI SUBBANNA

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/737 ,  H01L27/08

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.